arm.h (CLASS_LIKELY_SPILLED_P): Define.

	* arm.h (CLASS_LIKELY_SPILLED_P): Define.
testsuite
	* gcc.dg/spill-1.c: New test.

From-SVN: r80519

gcc/ChangeLog

 2004-04-08  Paul Brook  <paul@codesourcery.com>
 
+	* arm.h (CLASS_LIKELY_SPILLED_P): Define.
+
+2004-04-08  Paul Brook  <paul@codesourcery.com>
+
 	* explow.c (promote_mode): Use PROMOTE_FUNCTION_MODE instead of
 	PROMOTE_FOR_CALL_ONLY.
 	* config/arm/arm-protos.h (arm_function_value): Declare.

gcc/config/arm/arm.h

@@ -1378,6 +1378,13 @@ enum reg_class
      || reg_classes_intersect_p (VFP_REGS, (CLASS))	\
    : 0)
 
+/* We need to define this for LO_REGS on thumb.  Otherwise we can end up
+   using r0-r4 for function arguments, r7 for the stack frame and don't
+   have enough left over to do doubleword arithmetic.  */
+#define CLASS_LIKELY_SPILLED_P(CLASS)	\
+    ((TARGET_THUMB && (CLASS) == LO_REGS)	\
+     || (CLASS) == CC_REG)
+				      
 /* The class value for index registers, and the one for base regs.  */
 #define INDEX_REG_CLASS  (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
 #define BASE_REG_CLASS   (TARGET_THUMB ? LO_REGS : GENERAL_REGS)

gcc/testsuite/ChangeLog

+2004-04-08  Paul Brook  <paul@codesourcery.com>
+
+	* gcc.dg/spill-1.c: New test.
+
 2004-04-08  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
 
 	* gcc.dg/torture/builtin-ctype-2.c: New test.

gcc/testsuite/gcc.dg/spill-1.c

+/* This caused an ICE during register spilling when targeting thumb.
+   There are 8 registers available for arithmetic operations (r0-r7)
+   r7 is the frame pointer, and r0-r3 are used to pass arguments.
+   Combine was extending the lives of the arguments (in r0-r3) up until the
+   call to z. This leaves only 3 regs free which isn't enough to preform the
+   doubleword addition.  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -fno-omit-frame-pointer" } */
+void z(int);
+int foo(int a, int b, int c, int d, long long *q) 
+{ 
+  *q=*q+1; 
+  z (a+b+c+d); 
+}
+