Reformat some code; Add support for generating PLWA with offsets whose bottom 2 bits are non-zero.

2019-10-23  Michael Meissner  <meissner@linux.ibm.com>

	* config/rs6000/rs6000.md (mov<mode>_64bit_dm): Reformat.
	(movtd_64bit_nodm): Reformat.
	(mov<mode>_32bit): Reformat.
	(mov<mode>_softfloat): Reformat.
	(FMOVE128_GPR splitter): Reformat.
	(DIFD splitter): Reformat.
	(TI2 splitter): Reformat.
	* config/rs6000/predicates.md (lwa_operand): If the bottom two
	bits of the offset for the memory address are non-zero, use PLWA
	if prefixed instructions are available.

From-SVN: r277349

gcc/ChangeLog

+2019-10-23  Michael Meissner  <meissner@linux.ibm.com>
+
+	* config/rs6000/rs6000.md (mov<mode>_64bit_dm): Reformat.
+	(movtd_64bit_nodm): Reformat.
+	(mov<mode>_32bit): Reformat.
+	(mov<mode>_softfloat): Reformat.
+	(FMOVE128_GPR splitter): Reformat.
+	(DIFD splitter): Reformat.
+	(TI2 splitter): Reformat.
+	* config/rs6000/predicates.md (lwa_operand): If the bottom two
+	bits of the offset for the memory address are non-zero, use PLWA
+	if prefixed instructions are available.
+
 2019-10-23  Jan Hubicka  <hubicka@ucw.cz>
 
 	* lto-streamer-out.c (cmp_symbol_files): Watch for overflow.

gcc/config/rs6000/predicates.md

@@ -932,6 +932,14 @@
     return false;
 
   addr = XEXP (inner, 0);
+
+  /* The LWA instruction uses the DS-form instruction format which requires
+     that the bottom two bits of the offset must be 0.  The prefixed PLWA does
+     not have this restriction.  While the actual load from memory is 32-bits,
+     we pass in DImode here to test for using a DS instruction.  */
+  if (address_is_prefixed (addr, DImode, NON_PREFIXED_DS))
+    return true;
+
   if (GET_CODE (addr) == PRE_INC
       || GET_CODE (addr) == PRE_DEC
       || (GET_CODE (addr) == PRE_MODIFY

gcc/config/rs6000/rs6000.md

@@ -7761,7 +7761,10 @@
   "#"
   "&& reload_completed"
   [(pc)]
-{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
+{
+  rs6000_split_multireg_move (operands[0], operands[1]);
+  DONE;
+}
   [(set_attr "length" "8")
    (set_attr "isa" "*,*,*,*,*,*,*,*,p8v,p8v")])
 
@@ -7774,7 +7777,10 @@
   "#"
   "&& reload_completed"
   [(pc)]
-{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
+{
+  rs6000_split_multireg_move (operands[0], operands[1]);
+  DONE;
+}
   [(set_attr "length" "8,8,8,12,12,8")])
 
 (define_insn_and_split "*mov<mode>_32bit"
@@ -7789,7 +7795,10 @@
   "#"
   "&& reload_completed"
   [(pc)]
-{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
+{
+  rs6000_split_multireg_move (operands[0], operands[1]);
+  DONE;
+}
   [(set_attr "length" "8,8,8,8,20,20,16")])
 
 (define_insn_and_split "*mov<mode>_softfloat"
@@ -7801,7 +7810,10 @@
   "#"
   "&& reload_completed"
   [(pc)]
-{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
+{
+  rs6000_split_multireg_move (operands[0], operands[1]);
+  DONE;
+}
   [(set_attr_alternative "length"
        [(if_then_else (match_test "TARGET_POWERPC64")
 	    (const_string "8")
@@ -8593,7 +8605,10 @@
        || (!vsx_register_operand (operands[0], <MODE>mode)
            && !vsx_register_operand (operands[1], <MODE>mode)))"
   [(pc)]
-{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
+{
+  rs6000_split_multireg_move (operands[0], operands[1]);
+  DONE;
+})
 
 ;; Move SFmode to a VSX from a GPR register.  Because scalar floating point
 ;; type is stored internally as double precision in the VSX registers, we have
@@ -8783,7 +8798,10 @@
    && gpr_or_gpr_p (operands[0], operands[1])
    && !direct_move_p (operands[0], operands[1])"
   [(pc)]
-{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
+{
+  rs6000_split_multireg_move (operands[0], operands[1]);
+  DONE;
+})
 
 ;;              GPR store  GPR load   GPR move   GPR li     GPR lis     GPR #
 ;;              FPR store  FPR load   FPR move   AVX store  AVX store   AVX load
@@ -9009,7 +9027,10 @@
    && !direct_move_p (operands[0], operands[1])
    && !quad_load_store_p (operands[0], operands[1])"
   [(pc)]
-{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
+{
+  rs6000_split_multireg_move (operands[0], operands[1]);
+  DONE;
+})
 
 (define_expand "setmemsi"
   [(parallel [(set (match_operand:BLK 0 "")