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riscv-gcc-1
Commit cb8cc086 by Michael Meissner Committed by David Edelsohn
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rs6000.md ({add,sub}si3 `.'): Add alternatives to use CR other than cr0. 

	* rs6000.md ({add,sub}si3 `.'): Add alternatives to use CR other
	than cr0.

From-SVN: r25267
parent d5355be3
Showing with 123 additions and 37 deletions
gcc/ChangeLog
Wed Feb 17 14:04:18 1999 Michael Meissner <meissner@cygnus.com>
* rs6000.md ({add,sub}si3 `.'): Add alternatives to use CR other
than cr0.
Wed Feb 17 16:59:28 1999 J"orn Rennecke <amylaar@cygnus.co.uk>
* loop.c (strength_reduce): Don't move giv insn for biv turned giv
......
gcc/config/rs6000/rs6000.md
......@@ -926,29 +926,67 @@
[(set_attr "length" "4,4,4,4")])
(define_insn "*addsi3_internal2"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
(compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
(match_operand:SI 2 "reg_or_short_operand" "r,I"))
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
(compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
(match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
(const_int 0)))
(clobber (match_scratch:SI 3 "=r,r"))]
(clobber (match_scratch:SI 3 "=r,r,r,r"))]
""
"@
{cax.|add.} %3,%1,%2
{ai.|addic.} %3,%1,%2"
[(set_attr "type" "compare")])
{ai.|addic.} %3,%1,%2
#
#"
[(set_attr "type" "compare")
(set_attr "length" "4,4,8,8")])
(define_split
[(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
(compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
(match_operand:SI 2 "reg_or_short_operand" ""))
(const_int 0)))
(clobber (match_scratch:SI 3 ""))]
"reload_completed"
[(set (match_dup 3)
(plus:SI (match_dup 1)
(match_dup 2)))
(set (match_dup 0)
(compare:CC (match_dup 3)
(const_int 0)))]
"")
(define_insn "*addsi3_internal3"
[(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
(compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
(match_operand:SI 2 "reg_or_short_operand" "r,I"))
[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
(compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
(match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(plus:SI (match_dup 1) (match_dup 2)))]
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
(plus:SI (match_dup 1)
(match_dup 2)))]
""
"@
{cax.|add.} %0,%1,%2
{ai.|addic.} %0,%1,%2"
[(set_attr "type" "compare")])
{ai.|addic.} %0,%1,%2
#
#"
[(set_attr "type" "compare")
(set_attr "length" "4,4,8,8")])
(define_split
[(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
(compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
(match_operand:SI 2 "reg_or_short_operand" ""))
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "")
(plus:SI (match_dup 1) (match_dup 2)))]
"reload_completed"
[(set (match_dup 0)
(plus:SI (match_dup 1)
(match_dup 2)))
(set (match_dup 3)
(compare:CC (match_dup 0)
(const_int 0)))]
"")
;; Split an add that we can't do in one insn into two insns, each of which
;; does one 16-bit part. This is used by combine. Note that the low-order
......@@ -1015,46 +1053,89 @@
subfic %0,%2,%1")
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
(compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "gpc_reg_operand" "r"))
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
(compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "gpc_reg_operand" "r,r"))
(const_int 0)))
(clobber (match_scratch:SI 3 "=r"))]
(clobber (match_scratch:SI 3 "=r,r"))]
"! TARGET_POWERPC"
"{sf.|subfc.} %3,%2,%1"
[(set_attr "type" "compare")])
"@
{sf.|subfc.} %3,%2,%1
#"
[(set_attr "type" "compare")
(set_attr "length" "4,8")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
(compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "gpc_reg_operand" "r"))
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
(compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "gpc_reg_operand" "r,r"))
(const_int 0)))
(clobber (match_scratch:SI 3 "=r"))]
(clobber (match_scratch:SI 3 "=r,r"))]
"TARGET_POWERPC"
"subf. %3,%2,%1"
[(set_attr "type" "compare")])
"@
subf. %3,%2,%1
#"
[(set_attr "type" "compare")
(set_attr "length" "4,8")])
(define_split
[(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
(compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
(match_operand:SI 2 "gpc_reg_operand" ""))
(const_int 0)))
(clobber (match_scratch:SI 3 ""))]
"reload_completed"
[(set (match_dup 3)
(minus:SI (match_dup 1)
(match_dup 2)))
(set (match_dup 0)
(compare:CC (match_dup 3)
(const_int 0)))]
"")
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
(compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "gpc_reg_operand" "r"))
[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
(compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "gpc_reg_operand" "r,r"))
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(minus:SI (match_dup 1) (match_dup 2)))]
"! TARGET_POWERPC"
"{sf.|subfc.} %0,%2,%1"
[(set_attr "type" "compare")])
"@
{sf.|subfc.} %0,%2,%1
#"
[(set_attr "type" "compare")
(set_attr "length" "4,8")])
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
(compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "gpc_reg_operand" "r"))
[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
(compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "gpc_reg_operand" "r,r"))
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(minus:SI (match_dup 1) (match_dup 2)))]
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(minus:SI (match_dup 1)
(match_dup 2)))]
"TARGET_POWERPC"
"subf. %0,%2,%1"
[(set_attr "type" "compare")])
[(set_attr "type" "compare")
(set_attr "length" "4,8")])
(define_split
[(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
(compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
(match_operand:SI 2 "gpc_reg_operand" ""))
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "")
(minus:SI (match_dup 1)
(match_dup 2)))]
"reload_completed"
[(set (match_dup 0)
(minus:SI (match_dup 1)
(match_dup 2)))
(set (match_dup 3)
(compare:CC (match_dup 0)
(const_int 0)))]
"")
(define_expand "subsi3"
[(set (match_operand:SI 0 "gpc_reg_operand" "")
......
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