mips.md (move_type): Replace mfhilo and mthilo with mflo and mtlo.

gcc/
	* config/mips/mips.md (move_type): Replace mfhilo and mthilo
	with mflo and mtlo.
	(type): Split mfhilo into mfhi and mflo.  Split mthilo into mthi
	and mtlo.  Adjust move_type->type mapping.
	(may_clobber_hilo): Split mthilo into mthi and mtlo.
	(*movdi_32bit, *movdi_32bit_mips16, *movdi_64bit, *movdi_64bit_mips16)
	(*mov<mode>_internal, *mov<mode>_mips16, *movhi_internal)
	(*movhi_mips16, *movqi_internal, *movqi_mips16): Use mtlo and mflo
	instead of mthilo and mfhilo.
	(mfhi<GPR:mode>_<HILO:mode>): Use mfhi instead of mfhilo.
	(mthi<GPR:mode>_<HILO:mode>): Use mthi instead of mthilo.
	* config/mips/mips-dsp.md (mips_extr_w, mips_extr_r_w, mips_extr_rs_w)
	(mips_extr_s_h, mips_extp, mips_extpdp, mips_shilo, mips_mthlip):
	Use mflo instead of mfhilo.
	* config/mips/10000.md (r10k_arith): Split mthilo.
	(r10k_mfhi, r10k_mflo): Use mfhi and mflo directly.
	* config/mips/sb1.md (ir_sb1_mfhi, ir_sb1_mflo): Likewise.
	(ir_sb1_mthilo): Split mthilo into mthi and mtlo.
	* config/mips/20kc.md (r20kc_imthilo, r20kc_imfhilo): Split
	mthilo and mfhilo.
	* config/mips/24k.md (r24k_int_mfhilo, r24k_int_mthilo): Likewise.
	* config/mips/4130.md (vr4130_class, vr4130_mfhilo, vr4130_mthilo):
	Likewise.
	* config/mips/4k.md (r4k_int_mthilo, r4k_int_mfhilo): Likewise.
	* config/mips/5400.md (ir_vr54_hilo): Likewise.
	* config/mips/5500.md (ir_vr55_mthilo, ir_vr55_mfhilo): Likewise.
	* config/mips/5k.md (r5k_int_mthilo, r5k_int_mfhilo): Likewise.
	* config/mips/7000.md (rm7_mthilo, rm7_mfhilo): Likewise.
	* config/mips/74k.md (r74k_int_mfhilo, r74k_int_mthilo): Likewise.
	* config/mips/9000.md (rm9k_mfhilo, rm9k_mthilo): Likewise.
	* config/mips/generic.md (generic_hilo): Likewise.
	* config/mips/loongson2ef.md (ls2_alu): Likewise.
	* config/mips/loongson3a.md (ls3a_mfhilo): Likewise.
	* config/mips/octeon.md (octeon_imul_o1, octeon_imul_o2)
	(octeon_mfhilo_o1, octeon_mfhilo_o2): Likewise.
	* config/mips/sr71k.md (ir_sr70_hilo): Likewise.
	* config/mips/xlr.md (xlr_hilo): Likewise.

From-SVN: r189496

gcc/ChangeLog

+2012-07-15  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* config/mips/mips.md (move_type): Replace mfhilo and mthilo
+	with mflo and mtlo.
+	(type): Split mfhilo into mfhi and mflo.  Split mthilo into mthi
+	and mtlo.  Adjust move_type->type mapping.
+	(may_clobber_hilo): Split mthilo into mthi and mtlo.
+	(*movdi_32bit, *movdi_32bit_mips16, *movdi_64bit, *movdi_64bit_mips16)
+	(*mov<mode>_internal, *mov<mode>_mips16, *movhi_internal)
+	(*movhi_mips16, *movqi_internal, *movqi_mips16): Use mtlo and mflo
+	instead of mthilo and mfhilo.
+	(mfhi<GPR:mode>_<HILO:mode>): Use mfhi instead of mfhilo.
+	(mthi<GPR:mode>_<HILO:mode>): Use mthi instead of mthilo.
+	* config/mips/mips-dsp.md (mips_extr_w, mips_extr_r_w, mips_extr_rs_w)
+	(mips_extr_s_h, mips_extp, mips_extpdp, mips_shilo, mips_mthlip):
+	Use mflo instead of mfhilo.
+	* config/mips/10000.md (r10k_arith): Split mthilo.
+	(r10k_mfhi, r10k_mflo): Use mfhi and mflo directly.
+	* config/mips/sb1.md (ir_sb1_mfhi, ir_sb1_mflo): Likewise.
+	(ir_sb1_mthilo): Split mthilo into mthi and mtlo.
+	* config/mips/20kc.md (r20kc_imthilo, r20kc_imfhilo): Split
+	mthilo and mfhilo.
+	* config/mips/24k.md (r24k_int_mfhilo, r24k_int_mthilo): Likewise.
+	* config/mips/4130.md (vr4130_class, vr4130_mfhilo, vr4130_mthilo):
+	Likewise.
+	* config/mips/4k.md (r4k_int_mthilo, r4k_int_mfhilo): Likewise.
+	* config/mips/5400.md (ir_vr54_hilo): Likewise.
+	* config/mips/5500.md (ir_vr55_mthilo, ir_vr55_mfhilo): Likewise.
+	* config/mips/5k.md (r5k_int_mthilo, r5k_int_mfhilo): Likewise.
+	* config/mips/7000.md (rm7_mthilo, rm7_mfhilo): Likewise.
+	* config/mips/74k.md (r74k_int_mfhilo, r74k_int_mthilo): Likewise.
+	* config/mips/9000.md (rm9k_mfhilo, rm9k_mthilo): Likewise.
+	* config/mips/generic.md (generic_hilo): Likewise.
+	* config/mips/loongson2ef.md (ls2_alu): Likewise.
+	* config/mips/loongson3a.md (ls3a_mfhilo): Likewise.
+	* config/mips/octeon.md (octeon_imul_o1, octeon_imul_o2)
+	(octeon_mfhilo_o1, octeon_mfhilo_o2): Likewise.
+	* config/mips/sr71k.md (ir_sr70_hilo): Likewise.
+	* config/mips/xlr.md (xlr_hilo): Likewise.
+
 2012-07-14  Andrew Stubbs  <ams@codesourcery.com>
 	    Sandra Loosemore  <sandra@codesourcery.com>
 

gcc/config/mips/10000.md

@@ -68,21 +68,19 @@
 ;; Miscellaneous arith goes here too (this is a guess).
 (define_insn_reservation "r10k_arith" 1
   (and (eq_attr "cpu" "r10000")
-       (eq_attr "type" "arith,mthilo,slt,clz,const,nop,trap,logical"))
+       (eq_attr "type" "arith,mthi,mtlo,slt,clz,const,nop,trap,logical"))
   "r10k_alu1 | r10k_alu2")
 
 ;; We treat mfhilo differently, because we need to know when
 ;; it's HI and when it's LO.
 (define_insn_reservation "r10k_mfhi" 1
   (and (eq_attr "cpu" "r10000")
-       (and (eq_attr "type" "mfhilo")
-            (not (match_operand 1 "lo_operand"))))
+       (eq_attr "type" "mfhi"))
   "r10k_alu1 | r10k_alu2")
 
 (define_insn_reservation "r10k_mflo" 1
   (and (eq_attr "cpu" "r10000")
-       (and (eq_attr "type" "mfhilo")
-            (match_operand 1 "lo_operand")))
+       (eq_attr "type" "mflo"))
   "r10k_alu1 | r10k_alu2")
 
 

gcc/config/mips/20kc.md

@@ -195,12 +195,12 @@
 ;; cycle latency.  Repeat rate is 3 for both.
 (define_insn_reservation "r20kc_imthilo" 3 
 			 (and (eq_attr "cpu" "20kc")
-			      (eq_attr "type" "mthilo"))
+			      (eq_attr "type" "mthi,mtlo"))
 			 "r20kc_impydiv+(r20kc_impydiv_iter*3)")
 
 (define_insn_reservation "r20kc_imfhilo" 1
 			 (and (eq_attr "cpu" "20kc")
-			      (eq_attr "type" "mfhilo"))
+			      (eq_attr "type" "mfhi,mflo"))
 			 "r20kc_impydiv+(r20kc_impydiv_iter*3)")
 
 ;; Move to fp coprocessor.

gcc/config/mips/24k.md

@@ -94,13 +94,13 @@
 ;; mfhi, mflo, mflhxu - deliver result to gpr in 5 cycles
 (define_insn_reservation "r24k_int_mfhilo" 5
   (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
-       (eq_attr "type" "mfhilo"))
+       (eq_attr "type" "mfhi,mflo"))
   "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
 
 ;; mthi, mtlo, mtlhx - deliver result to hi/lo, thence madd, handled as bypass
 (define_insn_reservation "r24k_int_mthilo" 1
   (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
-       (eq_attr "type" "mthilo"))
+       (eq_attr "type" "mthi,mtlo"))
   "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
 
 ;; div - default to 36 cycles for 32bit operands.  Faster for 24bit, 16bit and

gcc/config/mips/4130.md

@@ -72,7 +72,7 @@
   (cond [(eq_attr "type" "load,store")
 	 (const_string "mem")
 
-	 (eq_attr "type" "mfhilo,mthilo,imul,imul3,imadd,idiv")
+	 (eq_attr "type" "mfhi,mflo,mthi,mtlo,imul,imul3,imadd,idiv")
 	 (const_string "mul")]
 	(const_string "alu")))
 
@@ -98,12 +98,12 @@
 
 (define_insn_reservation "vr4130_mfhilo" 3
   (and (eq_attr "cpu" "r4130")
-       (eq_attr "type" "mfhilo"))
+       (eq_attr "type" "mfhi,mflo"))
   "vr4130_muldiv")
 
 (define_insn_reservation "vr4130_mthilo" 1
   (and (eq_attr "cpu" "r4130")
-       (eq_attr "type" "mthilo"))
+       (eq_attr "type" "mthi,mtlo"))
   "vr4130_muldiv")
 
 ;; The product is available in LO & HI after one cycle.  Moving the result

gcc/config/mips/4k.md

@@ -114,13 +114,13 @@
 ;; Move to HI/LO -> MADD/MSUB,MFHI/MFLO has a 1 cycle latency.
 (define_insn_reservation "r4k_int_mthilo" 1
   (and (eq_attr "cpu" "4kc,4kp")
-       (eq_attr "type" "mthilo"))
+       (eq_attr "type" "mthi,mtlo"))
   "r4k_ixu_arith+r4k_ixu_mpydiv")
 
 ;; Move from HI/LO -> integer operation has a 2 cycle latency.
 (define_insn_reservation "r4k_int_mfhilo" 2
   (and (eq_attr "cpu" "4kc,4kp")
-       (eq_attr "type" "mfhilo"))
+       (eq_attr "type" "mfhi,mflo"))
   "r4k_ixu_arith+r4k_ixu_mpydiv")
 
 ;; All other integer insns.

gcc/config/mips/5400.md

@@ -73,7 +73,7 @@
 
 (define_insn_reservation "ir_vr54_hilo" 1
   (and (eq_attr "cpu" "r5400")
-       (eq_attr "type" "mthilo,mfhilo"))
+       (eq_attr "type" "mthi,mtlo,mfhi,mflo"))
   "vr54_dp0|vr54_dp1")
 
 (define_insn_reservation "ir_vr54_arith" 1

gcc/config/mips/5500.md

@@ -84,12 +84,12 @@
 
 (define_insn_reservation "ir_vr55_mthilo" 1
   (and (eq_attr "cpu" "r5500")
-       (eq_attr "type" "mthilo"))
+       (eq_attr "type" "mthi,mtlo"))
   "vr55_mac")
 
 (define_insn_reservation "ir_vr55_mfhilo" 5
   (and (eq_attr "cpu" "r5500")
-       (eq_attr "type" "mfhilo"))
+       (eq_attr "type" "mfhi,mflo"))
   "vr55_mac")
 
 ;; The default latency is for the GPR result of a mul.  Bypasses handle the

gcc/config/mips/5k.md

@@ -88,13 +88,13 @@
 ;; Move to HI/LO -> MADD/MSUB,MFHI/MFLO has a 1 cycle latency.
 (define_insn_reservation "r5k_int_mthilo" 1
   (and (eq_attr "cpu" "5kc,5kf")
-       (eq_attr "type" "mthilo"))
+       (eq_attr "type" "mthi,mtlo"))
   "r5k_ixu_arith+r5k_ixu_mpydiv")
 
 ;; Move from HI/LO -> integer operation has a 2 cycle latency.
 (define_insn_reservation "r5k_int_mfhilo" 2
   (and (eq_attr "cpu" "5kc,5kf")
-       (eq_attr "type" "mfhilo"))
+       (eq_attr "type" "mfhi,mflo"))
   "r5k_ixu_arith+r5k_ixu_mpydiv")
 
 ;; All other integer insns.

gcc/config/mips/7000.md

@@ -134,12 +134,12 @@
 ;; Move to/from HI/LO.
 (define_insn_reservation "rm7_mthilo" 3
   (and (eq_attr "cpu" "r7000")
-       (eq_attr "type" "mthilo"))
+       (eq_attr "type" "mthi,mtlo"))
   "rm7_impydiv")
 
 (define_insn_reservation "rm7_mfhilo" 1
   (and (eq_attr "cpu" "r7000")
-       (eq_attr "type" "mfhilo"))
+       (eq_attr "type" "mfhi,mflo"))
   "rm7_impydiv")
 
 ;; Move to/from fp coprocessor.

gcc/config/mips/74k.md

@@ -80,13 +80,13 @@
 ;; mfhi, mflo, mflhxu - deliver result to gpr in 7 cycles
 (define_insn_reservation "r74k_int_mfhilo" 7
   (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
-       (eq_attr "type" "mfhilo"))
+       (eq_attr "type" "mfhi,mflo"))
   "r74k_alu+r74k_mul")
 
 ;; mthi, mtlo, mtlhx - deliver result to hi/lo, thence madd, handled as bypass
 (define_insn_reservation "r74k_int_mthilo" 7
   (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
-       (eq_attr "type" "mthilo"))
+       (eq_attr "type" "mthi,mtlo"))
   "r74k_alu+r74k_mul")
 
 ;; div - default to 50 cycles for 32bit operands.  Faster for 8 bit,

gcc/config/mips/9000.md

@@ -87,12 +87,12 @@
 
 (define_insn_reservation "rm9k_mfhilo" 1
   (and (eq_attr "cpu" "r9000")
-       (eq_attr "type" "mfhilo"))
+       (eq_attr "type" "mfhi,mflo"))
   "rm9k_f_int")
 
 (define_insn_reservation "rm9k_mthilo" 5
   (and (eq_attr "cpu" "r9000")
-       (eq_attr "type" "mthilo"))
+       (eq_attr "type" "mthi,mtlo"))
   "rm9k_f_int")
 
 (define_insn_reservation "rm9k_xfer" 2

gcc/config/mips/generic.md

@@ -43,7 +43,7 @@
   "alu")
 
 (define_insn_reservation "generic_hilo" 1
-  (eq_attr "type" "mfhilo,mthilo")
+  (eq_attr "type" "mfhi,mflo,mthi,mtlo")
   "imuldiv*3")
 
 (define_insn_reservation "generic_imul" 17

gcc/config/mips/loongson2ef.md

@@ -154,8 +154,8 @@
 ;; Reservation for integer instructions.
 (define_insn_reservation "ls2_alu" 2
   (and (eq_attr "cpu" "loongson_2e,loongson_2f")
-       (eq_attr "type" "arith,condmove,const,logical,mfhilo,move,
-                        mthilo,nop,shift,signext,slt"))
+       (eq_attr "type" "arith,condmove,const,logical,mfhi,mflo,move,
+                        mthi,mtlo,nop,shift,signext,slt"))
   "ls2_alu")
 
 ;; Reservation for branch instructions.

gcc/config/mips/loongson3a.md

@@ -53,7 +53,7 @@
 
 (define_insn_reservation "ls3a_mfhilo" 1
   (and (eq_attr "cpu" "loongson_3a")
-       (eq_attr "type" "mfhilo,mthilo"))
+       (eq_attr "type" "mfhi,mflo,mthi,mtlo"))
   "ls3a_alu2")
 
 ;; Operation imul3nc is fully pipelined.

gcc/config/mips/mips-dsp.md

@@ -909,7 +909,7 @@
     }
   return "extrv.w\t%0,%q1,%2";
 }
-  [(set_attr "type"	"mfhilo")
+  [(set_attr "type"	"mflo")
    (set_attr "mode"	"SI")])
 
 (define_insn "mips_extr_r_w"
@@ -930,7 +930,7 @@
     }
   return "extrv_r.w\t%0,%q1,%2";
 }
-  [(set_attr "type"	"mfhilo")
+  [(set_attr "type"	"mflo")
    (set_attr "mode"	"SI")])
 
 (define_insn "mips_extr_rs_w"
@@ -951,7 +951,7 @@
     }
   return "extrv_rs.w\t%0,%q1,%2";
 }
-  [(set_attr "type"	"mfhilo")
+  [(set_attr "type"	"mflo")
    (set_attr "mode"	"SI")])
 
 ;; EXTR*_S.H
@@ -973,7 +973,7 @@
     }
   return "extrv_s.h\t%0,%q1,%2";
 }
-  [(set_attr "type"	"mfhilo")
+  [(set_attr "type"	"mflo")
    (set_attr "mode"	"SI")])
 
 ;; EXTP*
@@ -996,7 +996,7 @@
     }
   return "extpv\t%0,%q1,%2";
 }
-  [(set_attr "type"	"mfhilo")
+  [(set_attr "type"	"mflo")
    (set_attr "mode"	"SI")])
 
 (define_insn "mips_extpdp"
@@ -1021,7 +1021,7 @@
     }
   return "extpdpv\t%0,%q1,%2";
 }
-  [(set_attr "type"	"mfhilo")
+  [(set_attr "type"	"mflo")
    (set_attr "mode"	"SI")])
 
 ;; SHILO*
@@ -1040,7 +1040,7 @@
     }
   return "shilov\t%q0,%2";
 }
-  [(set_attr "type"	"mfhilo")
+  [(set_attr "type"	"mflo")
    (set_attr "mode"	"SI")])
 
 ;; MTHLIP*
@@ -1056,7 +1056,7 @@
 			 (reg:CCDSP CCDSP_PO_REGNUM)] UNSPEC_MTHLIP))])]
   "ISA_HAS_DSP && !TARGET_64BIT"
   "mthlip\t%2,%q0"
-  [(set_attr "type"	"mfhilo")
+  [(set_attr "type"	"mflo")
    (set_attr "mode"	"SI")])
 
 ;; WRDSP

gcc/config/mips/mips.md

@@ -201,7 +201,7 @@
 ;; the split instructions; in some cases, it is more appropriate for the
 ;; scheduling type to be "multi" instead.
 (define_attr "move_type"
-  "unknown,load,fpload,store,fpstore,mtc,mfc,mthilo,mfhilo,move,fmove,
+  "unknown,load,fpload,store,fpstore,mtc,mfc,mtlo,mflo,move,fmove,
    const,constN,signext,ext_ins,logical,arith,sll0,andi,loadpool,
    shift_shift,lui_movf"
   (const_string "unknown"))
@@ -239,8 +239,10 @@
 ;; condmove	conditional moves
 ;; mtc		transfer to coprocessor
 ;; mfc		transfer from coprocessor
-;; mthilo	transfer to hi/lo registers
-;; mfhilo	transfer from hi/lo registers
+;; mthi		transfer to a hi register
+;; mtlo		transfer to a lo register
+;; mfhi		transfer from a hi register
+;; mflo		transfer from a lo register
 ;; const	load constant
 ;; arith	integer arithmetic instructions
 ;; logical      integer logical instructions
@@ -278,7 +280,7 @@
 ;; ghost	an instruction that produces no real code
 (define_attr "type"
   "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,
-   prefetch,prefetchx,condmove,mtc,mfc,mthilo,mfhilo,const,arith,logical,
+   prefetch,prefetchx,condmove,mtc,mfc,mthi,mtlo,mfhi,mflo,const,arith,logical,
    shift,slt,signext,clz,pop,trap,imul,imul3,imul3nc,imadd,idiv,idiv3,move,
    fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,
    frsqrt,frsqrt1,frsqrt2,multi,nop,ghost"
@@ -298,8 +300,8 @@
 	 (eq_attr "move_type" "fpstore") (const_string "fpstore")
 	 (eq_attr "move_type" "mtc") (const_string "mtc")
 	 (eq_attr "move_type" "mfc") (const_string "mfc")
-	 (eq_attr "move_type" "mthilo") (const_string "mthilo")
-	 (eq_attr "move_type" "mfhilo") (const_string "mfhilo")
+	 (eq_attr "move_type" "mtlo") (const_string "mtlo")
+	 (eq_attr "move_type" "mflo") (const_string "mflo")
 
 	 ;; These types of move are always single insns.
 	 (eq_attr "move_type" "fmove") (const_string "fmove")
@@ -475,7 +477,7 @@
 
 	  ;; Check for doubleword moves that are decomposed into two
 	  ;; instructions.
-	  (and (eq_attr "move_type" "mtc,mfc,mthilo,mfhilo,move")
+	  (and (eq_attr "move_type" "mtc,mfc,mtlo,mflo,move")
 	       (eq_attr "dword_mode" "yes"))
 	  (const_int 8)
 
@@ -557,7 +559,7 @@
 	      (match_test "TARGET_FIX_R4000"))
 	 (const_string "hilo")
 
-	 (and (eq_attr "type" "mfhilo")
+	 (and (eq_attr "type" "mfhi,mflo")
 	      (not (match_test "ISA_HAS_HILO_INTERLOCKS")))
 	 (const_string "hilo")]
 	(const_string "none")))
@@ -585,7 +587,7 @@
 ;; True if an instruction might assign to hi or lo when reloaded.
 ;; This is used by the TUNE_MACC_CHAINS code.
 (define_attr "may_clobber_hilo" "no,yes"
-  (if_then_else (eq_attr "type" "imul,imul3,imadd,idiv,mthilo")
+  (if_then_else (eq_attr "type" "imul,imul3,imadd,idiv,mthi,mtlo")
 		(const_string "yes")
 		(const_string "no")))
 
@@ -4115,7 +4117,7 @@
    && (register_operand (operands[0], DImode)
        || reg_or_0_operand (operands[1], DImode))"
   { return mips_output_move (operands[0], operands[1]); }
-  [(set_attr "move_type" "move,const,load,store,mthilo,mfhilo,mtc,fpload,mfc,fpstore,mtc,fpload,mfc,fpstore")
+  [(set_attr "move_type" "move,const,load,store,mtlo,mflo,mtc,fpload,mfc,fpstore,mtc,fpload,mfc,fpstore")
    (set_attr "mode" "DI")])
 
 (define_insn "*movdi_32bit_mips16"
@@ -4125,7 +4127,7 @@
    && (register_operand (operands[0], DImode)
        || register_operand (operands[1], DImode))"
   { return mips_output_move (operands[0], operands[1]); }
-  [(set_attr "move_type" "move,move,move,const,constN,load,store,mfhilo")
+  [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo")
    (set_attr "mode" "DI")])
 
 (define_insn "*movdi_64bit"
@@ -4135,7 +4137,7 @@
    && (register_operand (operands[0], DImode)
        || reg_or_0_operand (operands[1], DImode))"
   { return mips_output_move (operands[0], operands[1]); }
-  [(set_attr "move_type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mthilo,mfhilo,mtc,fpload,mfc,fpstore")
+  [(set_attr "move_type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mtlo,mflo,mtc,fpload,mfc,fpstore")
    (set_attr "mode" "DI")])
 
 (define_insn "*movdi_64bit_mips16"
@@ -4145,7 +4147,7 @@
    && (register_operand (operands[0], DImode)
        || register_operand (operands[1], DImode))"
   { return mips_output_move (operands[0], operands[1]); }
-  [(set_attr "move_type" "move,move,move,const,constN,const,loadpool,load,store,mfhilo")
+  [(set_attr "move_type" "move,move,move,const,constN,const,loadpool,load,store,mflo")
    (set_attr "mode" "DI")])
 
 ;; On the mips16, we can split ld $r,N($r) into an add and a load,
@@ -4213,7 +4215,7 @@
    && (register_operand (operands[0], <MODE>mode)
        || reg_or_0_operand (operands[1], <MODE>mode))"
   { return mips_output_move (operands[0], operands[1]); }
-  [(set_attr "move_type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mfc,mtc,mthilo,mfhilo,mtc,fpload,mfc,fpstore")
+  [(set_attr "move_type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mfc,mtc,mtlo,mflo,mtc,fpload,mfc,fpstore")
    (set_attr "mode" "SI")])
 
 (define_insn "*mov<mode>_mips16"
@@ -4223,7 +4225,7 @@
    && (register_operand (operands[0], <MODE>mode)
        || register_operand (operands[1], <MODE>mode))"
   { return mips_output_move (operands[0], operands[1]); }
-  [(set_attr "move_type" "move,move,move,const,constN,const,loadpool,load,store,mfhilo")
+  [(set_attr "move_type" "move,move,move,const,constN,const,loadpool,load,store,mflo")
    (set_attr "mode" "SI")])
 
 ;; On the mips16, we can split lw $r,N($r) into an add and a load,
@@ -4400,7 +4402,7 @@
    && (register_operand (operands[0], HImode)
        || reg_or_0_operand (operands[1], HImode))"
   { return mips_output_move (operands[0], operands[1]); }
-  [(set_attr "move_type" "move,const,load,store,mthilo,mfhilo")
+  [(set_attr "move_type" "move,const,load,store,mtlo,mflo")
    (set_attr "mode" "HI")])
 
 (define_insn "*movhi_mips16"
@@ -4410,7 +4412,7 @@
    && (register_operand (operands[0], HImode)
        || register_operand (operands[1], HImode))"
   { return mips_output_move (operands[0], operands[1]); }
-  [(set_attr "move_type" "move,move,move,const,constN,load,store,mfhilo")
+  [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo")
    (set_attr "mode" "HI")])
 
 ;; On the mips16, we can split lh $r,N($r) into an add and a load,
@@ -4475,7 +4477,7 @@
    && (register_operand (operands[0], QImode)
        || reg_or_0_operand (operands[1], QImode))"
   { return mips_output_move (operands[0], operands[1]); }
-  [(set_attr "move_type" "move,const,load,store,mthilo,mfhilo")
+  [(set_attr "move_type" "move,const,load,store,mtlo,mflo")
    (set_attr "mode" "QI")])
 
 (define_insn "*movqi_mips16"
@@ -4485,7 +4487,7 @@
    && (register_operand (operands[0], QImode)
        || register_operand (operands[1], QImode))"
   { return mips_output_move (operands[0], operands[1]); }
-  [(set_attr "move_type" "move,move,move,const,constN,load,store,mfhilo")
+  [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo")
    (set_attr "mode" "QI")])
 
 ;; On the mips16, we can split lb $r,N($r) into an add and a load,
@@ -4616,7 +4618,7 @@
    && (register_operand (operands[0], TImode)
        || reg_or_0_operand (operands[1], TImode))"
   "#"
-  [(set_attr "move_type" "move,const,load,store,mthilo,mfhilo")
+  [(set_attr "move_type" "move,const,load,store,mtlo,mflo")
    (set_attr "mode" "TI")])
 
 (define_insn "*movti_mips16"
@@ -4627,7 +4629,7 @@
    && (register_operand (operands[0], TImode)
        || register_operand (operands[1], TImode))"
   "#"
-  [(set_attr "move_type" "move,move,move,const,constN,load,store,mfhilo")
+  [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo")
    (set_attr "mode" "TI")])
 
 ;; 128-bit floating point moves
@@ -4734,7 +4736,7 @@
 		    UNSPEC_MFHI))]
   ""
   { return ISA_HAS_MACCHI ? "<GPR:d>macchi\t%0,%.,%." : "mfhi\t%0"; }
-  [(set_attr "move_type" "mfhilo")
+  [(set_attr "type" "mfhi")
    (set_attr "mode" "<GPR:MODE>")])
 
 ;; Set the high part of a HI/LO value, given that the low part has
@@ -4747,7 +4749,7 @@
 		     UNSPEC_MTHI))]
   ""
   "mthi\t%z1"
-  [(set_attr "move_type" "mthilo")
+  [(set_attr "type" "mthi")
    (set_attr "mode" "SI")])
 
 ;; Emit a doubleword move in which exactly one of the operands is

gcc/config/mips/octeon.md

@@ -83,22 +83,22 @@
 
 (define_insn_reservation "octeon_imul_o1" 2
   (and (eq_attr "cpu" "octeon")
-       (eq_attr "type" "imul,mthilo"))
+       (eq_attr "type" "imul,mthi,mtlo"))
   "(octeon_pipe0 | octeon_pipe1) + octeon_mult, octeon_mult")
 
 (define_insn_reservation "octeon_imul_o2" 1
   (and (eq_attr "cpu" "octeon2")
-       (eq_attr "type" "imul,mthilo"))
+       (eq_attr "type" "imul,mthi,mtlo"))
   "octeon_pipe1 + octeon_mult")
 
 (define_insn_reservation "octeon_mfhilo_o1" 5
   (and (eq_attr "cpu" "octeon")
-       (eq_attr "type" "mfhilo"))
+       (eq_attr "type" "mfhi,mflo"))
   "(octeon_pipe0 | octeon_pipe1) + octeon_mult")
 
 (define_insn_reservation "octeon_mfhilo_o2" 6
   (and (eq_attr "cpu" "octeon2")
-       (eq_attr "type" "mfhilo"))
+       (eq_attr "type" "mfhi,mflo"))
   "octeon_pipe1 + octeon_mult")
 
 (define_insn_reservation "octeon_imadd_o1" 4

gcc/config/mips/sb1.md

@@ -295,21 +295,19 @@
 
 (define_insn_reservation "ir_sb1_mfhi" 1
   (and (eq_attr "cpu" "sb1,sb1a")
-       (and (eq_attr "type" "mfhilo")
-	    (not (match_operand 1 "lo_operand"))))
+       (eq_attr "type" "mfhi"))
   "sb1_ex1")
 
 (define_insn_reservation "ir_sb1_mflo" 1
   (and (eq_attr "cpu" "sb1,sb1a")
-       (and (eq_attr "type" "mfhilo")
-	    (match_operand 1 "lo_operand")))
+       (eq_attr "type" "mflo"))
   "sb1_ex1")
 
 ;; mt{hi,lo} to mul/div is 4 cycles.
 
 (define_insn_reservation "ir_sb1_mthilo" 4
   (and (eq_attr "cpu" "sb1,sb1a")
-       (eq_attr "type" "mthilo"))
+       (eq_attr "type" "mthi,mtlo"))
   "sb1_ex1")
 
 ;; mt{hi,lo} to mf{hi,lo} is 3 cycles.

gcc/config/mips/sr71k.md

@@ -201,7 +201,7 @@
 
 (define_insn_reservation "ir_sr70_hilo" 1
   (and (eq_attr "cpu" "sr71000")
-       (eq_attr "type" "mthilo,mfhilo"))
+       (eq_attr "type" "mthi,mtlo,mfhi,mflo"))
   "ri_insns")
 
 (define_insn_reservation "ir_sr70_arith" 1

gcc/config/mips/xlr.md

@@ -85,5 +85,5 @@
 
 (define_insn_reservation "xlr_hilo" 2
   (and (eq_attr "cpu" "xlr") 
-       (eq_attr "type" "mfhilo,mthilo"))
+       (eq_attr "type" "mfhi,mflo,mthi,mtlo"))
   "xlr_imuldiv_nopipe")