Commit cac52161 by Jozef Lawrynowicz

Revert: 2019-10-07 Jozef Lawrynowicz <jozef.l@mittosystems.com>

	* config/msp430/msp430.md: Revert: Group zero_extend* insns together.

From-SVN: r276680
parent 795fe3d2
2019-10-07 Jozef Lawrynowicz <jozef.l@mittosystems.com>
* config/msp430/msp430.md: Group zero_extend* insns together.
2019-10-07 Iain Sandoe <iain@sandoe.co.uk> 2019-10-07 Iain Sandoe <iain@sandoe.co.uk>
* config/darwin.c (machopic_output_indirection): Don't put * config/darwin.c (machopic_output_indirection): Don't put
......
...@@ -559,11 +559,15 @@ ...@@ -559,11 +559,15 @@
AND%X0\t#0xff, %0" AND%X0\t#0xff, %0"
) )
(define_insn "zero_extendqisi2" ;; Eliminate extraneous zero-extends mysteriously created by gcc.
[(set (match_operand:SI 0 "nonimmediate_operand" "=r") (define_peephole2
(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm")))] [(set (match_operand:HI 0 "register_operand")
"" (zero_extend:HI (match_operand:QI 1 "general_operand")))
"MOV%X1.B\t%1,%L0 { CLR\t%H0" (set (match_operand:HI 2 "register_operand")
(zero_extend:HI (match_operand:QI 3 "register_operand")))]
"REGNO (operands[0]) == REGNO (operands[2]) && REGNO (operands[2]) == REGNO (operands[3])"
[(set (match_dup 0)
(zero_extend:HI (match_dup 1)))]
) )
(define_insn "zero_extendhipsi2" (define_insn "zero_extendhipsi2"
...@@ -574,6 +578,40 @@ ...@@ -574,6 +578,40 @@
MOVX\t%1, %0 MOVX\t%1, %0
MOVX.A\t%1, %0" MOVX.A\t%1, %0"
) )
(define_insn "truncpsihi2"
[(set (match_operand:HI 0 "msp430_nonimmediate_operand" "=rm")
(truncate:HI (match_operand:PSI 1 "register_operand" "r")))]
""
"MOVX\t%1, %0"
)
(define_insn "extendhisi2"
[(set (match_operand:SI 0 "nonimmediate_operand" "=r")
(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r")))]
""
{ return msp430x_extendhisi (operands); }
)
(define_insn "extendhipsi2"
[(set (match_operand:PSI 0 "nonimmediate_operand" "=r")
(subreg:PSI (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0")) 0))]
"msp430x"
"RLAM.A #4, %0 { RRAM.A #4, %0"
)
;; Look for cases where integer/pointer conversions are suboptimal due
;; to missing patterns, despite us not having opcodes for these
;; patterns. Doing these manually allows for alternate optimization
;; paths.
(define_insn "zero_extendqisi2"
[(set (match_operand:SI 0 "nonimmediate_operand" "=r")
(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm")))]
""
"MOV%X1.B\t%1,%L0 { CLR\t%H0"
)
(define_insn "zero_extendhisi2" (define_insn "zero_extendhisi2"
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r") [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0,r")))] (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0,r")))]
...@@ -592,6 +630,22 @@ ...@@ -592,6 +630,22 @@
MOV.W\t%1,%0" MOV.W\t%1,%0"
) )
(define_insn "extend_and_shift1_hipsi2"
[(set (subreg:SI (match_operand:PSI 0 "nonimmediate_operand" "=r") 0)
(ashift:SI (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0"))
(const_int 1)))]
"msp430x"
"RLAM.A #4, %0 { RRAM.A #3, %0"
)
(define_insn "extend_and_shift2_hipsi2"
[(set (subreg:SI (match_operand:PSI 0 "nonimmediate_operand" "=r") 0)
(ashift:SI (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0"))
(const_int 2)))]
"msp430x"
"RLAM.A #4, %0 { RRAM.A #2, %0"
)
; Nasty - we are sign-extending a 20-bit PSI value in one register into ; Nasty - we are sign-extending a 20-bit PSI value in one register into
; two adjacent 16-bit registers to make an SI value. There is no MSP430X ; two adjacent 16-bit registers to make an SI value. There is no MSP430X
; instruction that will do this, so we push the 20-bit value onto the stack ; instruction that will do this, so we push the 20-bit value onto the stack
...@@ -626,59 +680,6 @@ ...@@ -626,59 +680,6 @@
" "
) )
;; Eliminate extraneous zero-extends mysteriously created by gcc.
(define_peephole2
[(set (match_operand:HI 0 "register_operand")
(zero_extend:HI (match_operand:QI 1 "general_operand")))
(set (match_operand:HI 2 "register_operand")
(zero_extend:HI (match_operand:QI 3 "register_operand")))]
"REGNO (operands[0]) == REGNO (operands[2]) && REGNO (operands[2]) == REGNO (operands[3])"
[(set (match_dup 0)
(zero_extend:HI (match_dup 1)))]
)
(define_insn "truncpsihi2"
[(set (match_operand:HI 0 "msp430_nonimmediate_operand" "=rm")
(truncate:HI (match_operand:PSI 1 "register_operand" "r")))]
""
"MOVX\t%1, %0"
)
(define_insn "extendhisi2"
[(set (match_operand:SI 0 "nonimmediate_operand" "=r")
(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r")))]
""
{ return msp430x_extendhisi (operands); }
)
(define_insn "extendhipsi2"
[(set (match_operand:PSI 0 "nonimmediate_operand" "=r")
(subreg:PSI (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0")) 0))]
"msp430x"
"RLAM.A #4, %0 { RRAM.A #4, %0"
)
;; Look for cases where integer/pointer conversions are suboptimal due
;; to missing patterns, despite us not having opcodes for these
;; patterns. Doing these manually allows for alternate optimization
;; paths.
(define_insn "extend_and_shift1_hipsi2"
[(set (subreg:SI (match_operand:PSI 0 "nonimmediate_operand" "=r") 0)
(ashift:SI (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0"))
(const_int 1)))]
"msp430x"
"RLAM.A #4, %0 { RRAM.A #3, %0"
)
(define_insn "extend_and_shift2_hipsi2"
[(set (subreg:SI (match_operand:PSI 0 "nonimmediate_operand" "=r") 0)
(ashift:SI (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0"))
(const_int 2)))]
"msp430x"
"RLAM.A #4, %0 { RRAM.A #2, %0"
)
;; We also need to be able to sign-extend pointer types (eg ptrdiff_t). ;; We also need to be able to sign-extend pointer types (eg ptrdiff_t).
;; Since (we assume) pushing a 20-bit value onto the stack zero-extends ;; Since (we assume) pushing a 20-bit value onto the stack zero-extends
;; it, we use a different method here. ;; it, we use a different method here.
......
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