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Commit cab81ec0 by Richard Earnshaw Committed by Richard Earnshaw
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PR target/88799 Add +mp and +sec extensions to ARMv7-a 

Most armv7-a implementations support a number of basic extensions to
the architecture which are not particularly important to the compiler,
but can matter if code contains inline assembly.  This patch adds
support for these extensions, based on the capabilities that GAS
already provides for the appropriate CPUs.  For the purposes of
multilib selection we ignore these extensions entirely and map the
extended architecture versions down to the base versions we have
already support for.

gcc:
	PR target/88799
	* config/arm/arm-cpus.in (mp): New feature.
	(sec): New feature.
	(fgroup ARMv7ve): Add mp and sec features.
	(arch armv7-a): Add options to allow mp and sec extensions.
	(cpu generic-armv7-a): Add options to allow mp and sec extensions.
	(cpu cortex-a5, cpu cortex-7, cpu cortex-a9): Add mp and sec
	extenstions to the base architecture.
	(cpu cortex-a8): Add sec extension to the base architecture.
	(cpu marvell-pj4): Add mp and sec extensions to the base architecture.
	* config/arm/t-aprofile (MULTILIB_MATCHES): Map all armv7-a arch
	variants down to the base v7-a varaint.
	* config/arm/t-multilib (v7_a_arch_variants): New variable.
	* doc/invoke.texi (ARM Options): Add +mp and +sec to the list
	of permitted extensions for -march=armv7-a and for
	-mcpu=generic-armv7-a.

testsuite:
	* gcc.target/arm/multilib.exp (config "aprofile"): Add tests for
	mp and sec extensions to armv7-a.

From-SVN: r268072
parent 756721ba
Showing with 78 additions and 10 deletions
gcc/ChangeLog
2019-01-18 Richard Earnshaw <rearnsha@arm.com>
PR target/88799
* config/arm/arm-cpus.in (mp): New feature.
(sec): New feature.
(fgroup ARMv7ve): Add mp and sec features.
(arch armv7-a): Add options to allow mp and sec extensions.
(cpu generic-armv7-a): Add options to allow mp and sec extensions.
(cpu cortex-a5, cpu cortex-7, cpu cortex-a9): Add mp and sec
extenstions to the base architecture.
(cpu cortex-a8): Add sec extension to the base architecture.
(cpu marvell-pj4): Add mp and sec extensions to the base architecture.
* config/arm/t-aprofile (MULTILIB_MATCHES): Map all armv7-a arch
variants down to the base v7-a varaint.
* config/arm/t-multilib (v7_a_arch_variants): New variable.
* doc/invoke.texi (ARM Options): Add +mp and +sec to the list
of permitted extensions for -march=armv7-a and for
-mcpu=generic-armv7-a.
2019-01-18 Martin Liska <mliska@suse.cz> 2019-01-18 Martin Liska <mliska@suse.cz>
* params.def: Fix comment. * params.def: Fix comment.
......
gcc/config/arm/arm-cpus.in
...@@ -87,6 +87,12 @@ define feature armv7em ...@@ -87,6 +87,12 @@ define feature armv7em
# Architecture rel 7. # Architecture rel 7.
define feature armv7 define feature armv7
# MP extension to ArmV7-A
define feature mp
# SEC extension to ArmV7-A
define feature sec
# ARM division instructions. # ARM division instructions.
define feature adiv define feature adiv
...@@ -237,7 +243,7 @@ define fgroup ARMv6m armv4 thumb armv5t armv5te armv6 be8 ...@@ -237,7 +243,7 @@ define fgroup ARMv6m armv4 thumb armv5t armv5te armv6 be8
define fgroup ARMv7 ARMv6m thumb2 armv7 define fgroup ARMv7 ARMv6m thumb2 armv7
define fgroup ARMv7a ARMv7 notm armv6k define fgroup ARMv7a ARMv7 notm armv6k
define fgroup ARMv7ve ARMv7a adiv tdiv lpae define fgroup ARMv7ve ARMv7a adiv tdiv lpae mp sec
define fgroup ARMv7r ARMv7a tdiv define fgroup ARMv7r ARMv7a tdiv
define fgroup ARMv7m ARMv7 tdiv define fgroup ARMv7m ARMv7 tdiv
define fgroup ARMv7em ARMv7m armv7em define fgroup ARMv7em ARMv7m armv7em
...@@ -425,6 +431,8 @@ begin arch armv7-a ...@@ -425,6 +431,8 @@ begin arch armv7-a
base 7A base 7A
profile A profile A
isa ARMv7a isa ARMv7a
option mp add mp
option sec add sec
# fp => VFPv3-d16, simd => neon-vfpv3 # fp => VFPv3-d16, simd => neon-vfpv3
option fp add VFPv3 FP_DBL option fp add VFPv3 FP_DBL
optalias vfpv3-d16 fp optalias vfpv3-d16 fp
...@@ -968,6 +976,8 @@ begin cpu generic-armv7-a ...@@ -968,6 +976,8 @@ begin cpu generic-armv7-a
cname genericv7a cname genericv7a
tune flags LDSCHED tune flags LDSCHED
architecture armv7-a+fp architecture armv7-a+fp
option mp add mp
option sec add sec
option vfpv3-d16 add VFPv3 FP_DBL option vfpv3-d16 add VFPv3 FP_DBL
option vfpv3 add VFPv3 FP_D32 option vfpv3 add VFPv3 FP_D32
option vfpv3-d16-fp16 add VFPv3 FP_DBL fp16conv option vfpv3-d16-fp16 add VFPv3 FP_DBL fp16conv
...@@ -987,7 +997,7 @@ end cpu generic-armv7-a ...@@ -987,7 +997,7 @@ end cpu generic-armv7-a
begin cpu cortex-a5 begin cpu cortex-a5
cname cortexa5 cname cortexa5
tune flags LDSCHED tune flags LDSCHED
architecture armv7-a+neon-fp16 architecture armv7-a+mp+sec+neon-fp16
option nosimd remove ALL_SIMD option nosimd remove ALL_SIMD
option nofp remove ALL_FP option nofp remove ALL_FP
costs cortex_a5 costs cortex_a5
...@@ -1009,7 +1019,7 @@ end cpu cortex-a7 ...@@ -1009,7 +1019,7 @@ end cpu cortex-a7
begin cpu cortex-a8 begin cpu cortex-a8
cname cortexa8 cname cortexa8
tune flags LDSCHED tune flags LDSCHED
architecture armv7-a+simd architecture armv7-a+sec+simd
option nofp remove ALL_FP option nofp remove ALL_FP
costs cortex_a8 costs cortex_a8
vendor 41 vendor 41
...@@ -1019,7 +1029,7 @@ end cpu cortex-a8 ...@@ -1019,7 +1029,7 @@ end cpu cortex-a8
begin cpu cortex-a9 begin cpu cortex-a9
cname cortexa9 cname cortexa9
tune flags LDSCHED tune flags LDSCHED
architecture armv7-a+neon-fp16 architecture armv7-a+mp+sec+neon-fp16
option nosimd remove ALL_SIMD option nosimd remove ALL_SIMD
option nofp remove ALL_FP option nofp remove ALL_FP
costs cortex_a9 costs cortex_a9
...@@ -1140,7 +1150,7 @@ end cpu cortex-m3 ...@@ -1140,7 +1150,7 @@ end cpu cortex-m3
begin cpu marvell-pj4 begin cpu marvell-pj4
tune flags LDSCHED tune flags LDSCHED
architecture armv7-a architecture armv7-a+mp+sec
costs marvell_pj4 costs marvell_pj4
end cpu marvell-pj4 end cpu marvell-pj4
......
gcc/config/arm/t-aprofile
...@@ -49,14 +49,26 @@ MULTILIB_REQUIRED += mthumb/march=armv8-a+simd/mfloat-abi=softfp ...@@ -49,14 +49,26 @@ MULTILIB_REQUIRED += mthumb/march=armv8-a+simd/mfloat-abi=softfp
# Matches # Matches
# Arch Matches # Arch Matches
# Map all basic v7-a arch extensions to v7-a
MULTILIB_MATCHES += $(foreach ARCH, $(v7_a_arch_variants), \
march?armv7-a=march?armv7-a$(ARCH))
# Map all v7-a FP variants to vfpv3-d16 (+fp) # Map all v7-a FP variants to vfpv3-d16 (+fp)
MULTILIB_MATCHES += $(foreach ARCH, $(filter-out +fp, $(v7_a_nosimd_variants)), \ MULTILIB_MATCHES += $(foreach ARCH, $(filter-out +fp, $(v7_a_nosimd_variants)), \
march?armv7-a+fp=march?armv7-a$(ARCH)) march?armv7-a+fp=march?armv7-a$(ARCH))
MULTILIB_MATCHES += $(foreach ARCHVAR, $(v7_a_arch_variants), \
$(foreach ARCH, $(v7_a_nosimd_variants), \
march?armv7-a+fp=march?armv7-a$(ARCHVAR)$(ARCH)))
# Map all v7-a SIMD variants to neon-vfpv3 (+simd) # Map all v7-a SIMD variants to neon-vfpv3 (+simd)
MULTILIB_MATCHES += $(foreach ARCH, $(filter-out +simd, $(v7_a_simd_variants)), \ MULTILIB_MATCHES += $(foreach ARCH, $(filter-out +simd, $(v7_a_simd_variants)), \
march?armv7-a+simd=march?armv7-a$(ARCH)) march?armv7-a+simd=march?armv7-a$(ARCH))
MULTILIB_MATCHES += $(foreach ARCHVAR, $(v7_a_arch_variants), \
$(foreach ARCH, $(v7_a_simd_variants), \
march?armv7-a+simd=march?armv7-a$(ARCHVAR)$(ARCH)))
# Neither FP nor SIMD: map v7ve to v7-a # Neither FP nor SIMD: map v7ve to v7-a
MULTILIB_MATCHES += march?armv7-a=march?armv7ve MULTILIB_MATCHES += march?armv7-a=march?armv7ve
......
gcc/config/arm/t-multilib
...@@ -60,6 +60,7 @@ all_feat_combs = +$(firstword $(1)) \ ...@@ -60,6 +60,7 @@ all_feat_combs = +$(firstword $(1)) \
# Variables used. # Variables used.
all_early_arch := armv5tej armv6 armv6j armv6k armv6z armv6kz \ all_early_arch := armv5tej armv6 armv6j armv6k armv6z armv6kz \
armv6zk armv6t2 iwmmxt iwmmxt2 armv6zk armv6t2 iwmmxt iwmmxt2
v7_a_arch_variants := $(call all_feat_combs, mp sec)
v7_a_nosimd_variants := +fp +vfpv3 +vfpv3-d16-fp16 +vfpv3-fp16 +vfpv4-d16 +vfpv4 v7_a_nosimd_variants := +fp +vfpv3 +vfpv3-d16-fp16 +vfpv3-fp16 +vfpv4-d16 +vfpv4
v7_a_simd_variants := +simd +neon-fp16 +neon-vfpv4 v7_a_simd_variants := +simd +neon-fp16 +neon-vfpv4
v7ve_nosimd_variants := +vfpv3-d16 +vfpv3 +vfpv3-d16-fp16 +vfpv3-fp16 +fp +vfpv4 v7ve_nosimd_variants := +vfpv3-d16 +vfpv3 +vfpv3-d16-fp16 +vfpv3-fp16 +fp +vfpv4
......
gcc/doc/invoke.texi
...@@ -17090,6 +17090,12 @@ Disable the floating-point instructions. ...@@ -17090,6 +17090,12 @@ Disable the floating-point instructions.
@item armv7-a @item armv7-a
@table @samp @table @samp
@item +mp
The multiprocessing extension.
@item +sec
The security extension.
@item +fp @item +fp
The VFPv3 floating-point instructions, with 16 double-precision The VFPv3 floating-point instructions, with 16 double-precision
registers. The extension @samp{+vfpv3-d16} can be used as an alias registers. The extension @samp{+vfpv3-d16} can be used as an alias
...@@ -17518,11 +17524,11 @@ Enables the cryptographic instructions on @samp{cortex-a32}, ...@@ -17518,11 +17524,11 @@ Enables the cryptographic instructions on @samp{cortex-a32},
Additionally the @samp{generic-armv7-a} pseudo target defaults to Additionally the @samp{generic-armv7-a} pseudo target defaults to
VFPv3 with 16 double-precision registers. It supports the following VFPv3 with 16 double-precision registers. It supports the following
extension options: @samp{vfpv3-d16}, @samp{vfpv3}, extension options: @samp{mp}, @samp{sec}, @samp{vfpv3-d16},
@samp{vfpv3-d16-fp16}, @samp{vfpv3-fp16}, @samp{vfpv4-d16}, @samp{vfpv3}, @samp{vfpv3-d16-fp16}, @samp{vfpv3-fp16},
@samp{vfpv4}, @samp{neon}, @samp{neon-vfpv3}, @samp{neon-fp16}, @samp{vfpv4-d16}, @samp{vfpv4}, @samp{neon}, @samp{neon-vfpv3},
@samp{neon-vfpv4}. The meanings are the same as for the extensions to @samp{neon-fp16}, @samp{neon-vfpv4}. The meanings are the same as for
@option{-march=armv7-a}. the extensions to @option{-march=armv7-a}.
@option{-mcpu=generic-@var{arch}} is also permissible, and is @option{-mcpu=generic-@var{arch}} is also permissible, and is
equivalent to @option{-march=@var{arch} -mtune=generic-@var{arch}}. equivalent to @option{-march=@var{arch} -mtune=generic-@var{arch}}.
gcc/testsuite/ChangeLog
2019-01-18 Richard Earnshaw <rearnsha@arm.com>
PR target/88799
* gcc.target/arm/multilib.exp (config "aprofile"): Add tests for
mp and sec extensions to armv7-a.
2019-01-18 Martin Liska <mliska@suse.cz> 2019-01-18 Martin Liska <mliska@suse.cz>
* gcc.dg/no_profile_instrument_function-attr-1.c: Update * gcc.dg/no_profile_instrument_function-attr-1.c: Update
......
gcc/testsuite/gcc.target/arm/multilib.exp
...@@ -60,6 +60,16 @@ if {[multilib_config "aprofile"] } { ...@@ -60,6 +60,16 @@ if {[multilib_config "aprofile"] } {
{-mcpu=cortex-a7+nosimd -mfloat-abi=hard} "thumb/v7-a+fp/hard" {-mcpu=cortex-a7+nosimd -mfloat-abi=hard} "thumb/v7-a+fp/hard"
{-mcpu=cortex-a7+nofp -mfloat-abi=softfp} "thumb/v7-a/nofp" {-mcpu=cortex-a7+nofp -mfloat-abi=softfp} "thumb/v7-a/nofp"
{-mcpu=generic-armv7-a+vfpv4 -mfloat-abi=softfp} "thumb/v7-a+fp/softfp" {-mcpu=generic-armv7-a+vfpv4 -mfloat-abi=softfp} "thumb/v7-a+fp/softfp"
{-mcpu=generic-armv7-a+mp+vfpv4 -mfloat-abi=softfp} "thumb/v7-a+fp/softfp"
{-mcpu=generic-armv7-a+sec+vfpv4 -mfloat-abi=softfp} "thumb/v7-a+fp/softfp"
{-march=armv7-a+mp -mfloat-abi=softfp} "thumb/v7-a/nofp"
{-march=armv7-a+sec -mfloat-abi=softfp} "thumb/v7-a/nofp"
{-march=armv7-a+mp+sec -mfloat-abi=softfp} "thumb/v7-a/nofp"
{-march=armv7-a+sec+mp -mfloat-abi=softfp} "thumb/v7-a/nofp"
{-march=armv7-a+mp+vfpv4 -mfloat-abi=softfp} "thumb/v7-a+fp/softfp"
{-march=armv7-a+sec+fp -mfloat-abi=softfp} "thumb/v7-a+fp/softfp"
{-march=armv7-a+mp+sec+simd -mfloat-abi=softfp} "thumb/v7-a+simd/softfp"
{-march=armv7-a+sec+mp+vfpv3 -mfloat-abi=softfp} "thumb/v7-a+fp/softfp"
{-march=armv7ve+vfpv3 -mfloat-abi=hard} "thumb/v7-a+fp/hard" {-march=armv7ve+vfpv3 -mfloat-abi=hard} "thumb/v7-a+fp/hard"
{-march=armv7ve -mfloat-abi=softfp -mfpu=neon} "thumb/v7-a+simd/softfp" {-march=armv7ve -mfloat-abi=softfp -mfpu=neon} "thumb/v7-a+simd/softfp"
{-march=armv7ve -mfloat-abi=softfp -mfpu=neon-vfpv4} "thumb/v7ve+simd/softfp" {-march=armv7ve -mfloat-abi=softfp -mfpu=neon-vfpv4} "thumb/v7ve+simd/softfp"
...@@ -377,6 +387,10 @@ if {[multilib_config "aprofile"] } { ...@@ -377,6 +387,10 @@ if {[multilib_config "aprofile"] } {
{-mcpu=cortex-a15 -mfpu=neon-fp-armv8 -mfloat-abi=softfp -mthumb} "thumb/v7ve+simd/softfp" {-mcpu=cortex-a15 -mfpu=neon-fp-armv8 -mfloat-abi=softfp -mthumb} "thumb/v7ve+simd/softfp"
{-mcpu=cortex-a53 -mfpu=neon-fp-armv8 -mfloat-abi=softfp -mthumb} "thumb/v8-a+simd/softfp" {-mcpu=cortex-a53 -mfpu=neon-fp-armv8 -mfloat-abi=softfp -mthumb} "thumb/v8-a+simd/softfp"
{-march=armv7-a -mfpu=vfpv3-d16 -mfloat-abi=hard -mthumb} "thumb/v7-a+fp/hard" {-march=armv7-a -mfpu=vfpv3-d16 -mfloat-abi=hard -mthumb} "thumb/v7-a+fp/hard"
{-march=armv7-a+mp -mfpu=vfpv3-d16 -mfloat-abi=hard -mthumb} "thumb/v7-a+fp/hard"
{-march=armv7-a+sec -mfpu=vfpv3-d16 -mfloat-abi=hard -mthumb} "thumb/v7-a+fp/hard"
{-march=armv7-a+mp+sec -mfpu=vfpv3-d16 -mfloat-abi=hard -mthumb} "thumb/v7-a+fp/hard"
{-march=armv7-a+sec+mp -mfpu=vfpv3-d16 -mfloat-abi=hard -mthumb} "thumb/v7-a+fp/hard"
{-march=armv8-a -mfpu=vfpv3-d16 -mfloat-abi=hard -mthumb} "thumb/v8-a+simd/hard" {-march=armv8-a -mfpu=vfpv3-d16 -mfloat-abi=hard -mthumb} "thumb/v8-a+simd/hard"
{-march=armv7-a -mfpu=vfpv3-d16 -mfloat-abi=softfp -mthumb} "thumb/v7-a+fp/softfp" {-march=armv7-a -mfpu=vfpv3-d16 -mfloat-abi=softfp -mthumb} "thumb/v7-a+fp/softfp"
{-march=armv8-a -mfpu=vfpv3-d16 -mfloat-abi=softfp -mthumb} "thumb/v8-a+simd/softfp" {-march=armv8-a -mfpu=vfpv3-d16 -mfloat-abi=softfp -mthumb} "thumb/v8-a+simd/softfp"
......
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