Commit ca356f3a by Richard Earnshaw Committed by Richard Earnshaw

arm.c (thumb_expand_movstrqi): Rewrite to support SSA form.

* arm.c (thumb_expand_movstrqi): Rewrite to support SSA form.
(thumb_output_move_mem_multiple): Support new insn format.
* arm.md (movmem12b): Use SSA compatible format.
(movmem8b): Likewise.

From-SVN: r36809
parent cca0a211
2000-10-09 Richard Earnshaw <rearnsha@arm.com> 2000-10-09 Richard Earnshaw <rearnsha@arm.com>
* arm.c (thumb_expand_movstrqi): Rewrite to support SSA form.
(thumb_output_move_mem_multiple): Support new insn format.
* arm.md (movmem12b): Use SSA compatible format.
(movmem8b): Likewise.
2000-10-09 Richard Earnshaw <rearnsha@arm.com>
* arm.md (predicable): New attribute, default to "no". * arm.md (predicable): New attribute, default to "no".
(all patterns): Mark as predicable if appropriate. (all patterns): Mark as predicable if appropriate.
(conditional execution splits): Split using predication format. (conditional execution splits): Split using predication format.
......
...@@ -9543,38 +9543,38 @@ thumb_output_move_mem_multiple (n, operands) ...@@ -9543,38 +9543,38 @@ thumb_output_move_mem_multiple (n, operands)
switch (n) switch (n)
{ {
case 2: case 2:
if (REGNO (operands[2]) > REGNO (operands[3])) if (REGNO (operands[4]) > REGNO (operands[5]))
{ {
tmp = operands[2]; tmp = operands[4];
operands[2] = operands[3]; operands[4] = operands[5];
operands[3] = tmp; operands[5] = tmp;
} }
output_asm_insn ("ldmia\t%1!, {%2, %3}", operands); output_asm_insn ("ldmia\t%1!, {%4, %5}", operands);
output_asm_insn ("stmia\t%0!, {%2, %3}", operands); output_asm_insn ("stmia\t%0!, {%4, %5}", operands);
break; break;
case 3: case 3:
if (REGNO (operands[2]) > REGNO (operands[3])) if (REGNO (operands[4]) > REGNO (operands[5]))
{ {
tmp = operands[2]; tmp = operands[4];
operands[2] = operands[3]; operands[4] = operands[5];
operands[3] = tmp; operands[5] = tmp;
} }
if (REGNO (operands[3]) > REGNO (operands[4])) if (REGNO (operands[5]) > REGNO (operands[6]))
{ {
tmp = operands[3]; tmp = operands[5];
operands[3] = operands[4]; operands[5] = operands[6];
operands[4] = tmp; operands[6] = tmp;
} }
if (REGNO (operands[2]) > REGNO (operands[3])) if (REGNO (operands[4]) > REGNO (operands[5]))
{ {
tmp = operands[2]; tmp = operands[4];
operands[2] = operands[3]; operands[4] = operands[5];
operands[3] = tmp; operands[5] = tmp;
} }
output_asm_insn ("ldmia\t%1!, {%2, %3, %4}", operands); output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands);
output_asm_insn ("stmia\t%0!, {%2, %3, %4}", operands); output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands);
break; break;
default: default:
...@@ -9597,13 +9597,13 @@ thumb_expand_movstrqi (operands) ...@@ -9597,13 +9597,13 @@ thumb_expand_movstrqi (operands)
while (len >= 12) while (len >= 12)
{ {
emit_insn (gen_movmem12b (out, in)); emit_insn (gen_movmem12b (out, in, out, in));
len -= 12; len -= 12;
} }
if (len >= 8) if (len >= 8)
{ {
emit_insn (gen_movmem8b (out, in)); emit_insn (gen_movmem8b (out, in, out, in));
len -= 8; len -= 8;
} }
......
...@@ -5298,17 +5298,19 @@ ...@@ -5298,17 +5298,19 @@
;; Block-move insns ;; Block-move insns
(define_insn "movmem12b" (define_insn "movmem12b"
[(set (mem:SI (match_operand:SI 0 "register_operand" "+&l")) [(set (mem:SI (match_operand:SI 2 "register_operand" "0"))
(mem:SI (match_operand:SI 1 "register_operand" "+&l"))) (mem:SI (match_operand:SI 3 "register_operand" "1")))
(set (mem:SI (plus:SI (match_dup 0) (const_int 4))) (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
(mem:SI (plus:SI (match_dup 1) (const_int 4)))) (mem:SI (plus:SI (match_dup 3) (const_int 4))))
(set (mem:SI (plus:SI (match_dup 0) (const_int 8))) (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
(mem:SI (plus:SI (match_dup 1) (const_int 8)))) (mem:SI (plus:SI (match_dup 3) (const_int 8))))
(set (match_dup 0) (plus:SI (match_dup 0) (const_int 12))) (set (match_operand:SI 0 "register_operand" "=l")
(set (match_dup 1) (plus:SI (match_dup 1) (const_int 12))) (plus:SI (match_dup 2) (const_int 12)))
(clobber (match_scratch:SI 2 "=&l")) (set (match_operand:SI 1 "register_operand" "=l")
(clobber (match_scratch:SI 3 "=&l")) (plus:SI (match_dup 3) (const_int 12)))
(clobber (match_scratch:SI 4 "=&l"))] (clobber (match_scratch:SI 4 "=&l"))
(clobber (match_scratch:SI 5 "=&l"))
(clobber (match_scratch:SI 6 "=&l"))]
"TARGET_THUMB" "TARGET_THUMB"
"* return thumb_output_move_mem_multiple (3, operands);" "* return thumb_output_move_mem_multiple (3, operands);"
[(set_attr "length" "4") [(set_attr "length" "4")
...@@ -5318,14 +5320,16 @@ ...@@ -5318,14 +5320,16 @@
) )
(define_insn "movmem8b" (define_insn "movmem8b"
[(set (mem:SI (match_operand:SI 0 "register_operand" "+&l")) [(set (mem:SI (match_operand:SI 2 "register_operand" "0"))
(mem:SI (match_operand:SI 1 "register_operand" "+&l"))) (mem:SI (match_operand:SI 3 "register_operand" "1")))
(set (mem:SI (plus:SI (match_dup 0) (const_int 4))) (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
(mem:SI (plus:SI (match_dup 1) (const_int 4)))) (mem:SI (plus:SI (match_dup 3) (const_int 4))))
(set (match_dup 0) (plus:SI (match_dup 0) (const_int 8))) (set (match_operand:SI 0 "register_operand" "=l")
(set (match_dup 1) (plus:SI (match_dup 1) (const_int 8))) (plus:SI (match_dup 2) (const_int 8)))
(clobber (match_scratch:SI 2 "=&l")) (set (match_operand:SI 1 "register_operand" "=l")
(clobber (match_scratch:SI 3 "=&l"))] (plus:SI (match_dup 3) (const_int 8)))
(clobber (match_scratch:SI 4 "=&l"))
(clobber (match_scratch:SI 5 "=&l"))]
"TARGET_THUMB" "TARGET_THUMB"
"* return thumb_output_move_mem_multiple (2, operands);" "* return thumb_output_move_mem_multiple (2, operands);"
[(set_attr "length" "4") [(set_attr "length" "4")
......
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