Commit c9cdcaa5 by Bernd Schmidt Committed by Bernd Schmidt

iterators.md (qhs_extenddi_op): New mode_attr.

	* config/arm/iterators.md (qhs_extenddi_op): New mode_attr.
	(qhs_extenddi_cstr): Likewise.
	* config/arm/arm.md (zero_extend<mode>di2, extend<mode>di2): Use
	them for the source operand.

From-SVN: r164477
parent 903c31ee
2010-09-21 Bernd Schmidt <bernds@codesourcery.com>
* config/arm/iterators.md (qhs_extenddi_op): New mode_attr.
(qhs_extenddi_cstr): Likewise.
* config/arm/arm.md (zero_extend<mode>di2, extend<mode>di2): Use
them for the source operand.
2010-09-21 Uros Bizjak <ubizjak@gmail.com> 2010-09-21 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.c (ix86_split_ashl): Rename single_width variable * config/i386/i386.c (ix86_split_ashl): Rename single_width variable
......
...@@ -4042,7 +4042,8 @@ ...@@ -4042,7 +4042,8 @@
(define_insn "zero_extend<mode>di2" (define_insn "zero_extend<mode>di2"
[(set (match_operand:DI 0 "s_register_operand" "=r") [(set (match_operand:DI 0 "s_register_operand" "=r")
(zero_extend:DI (match_operand:QHSI 1 "nonimmediate_operand" "rm")))] (zero_extend:DI (match_operand:QHSI 1 "<qhs_extenddi_op>"
"<qhs_extenddi_cstr>")))]
"TARGET_32BIT <qhs_zextenddi_cond>" "TARGET_32BIT <qhs_zextenddi_cond>"
"#" "#"
[(set_attr "length" "8") [(set_attr "length" "8")
...@@ -4052,7 +4053,8 @@ ...@@ -4052,7 +4053,8 @@
(define_insn "extend<mode>di2" (define_insn "extend<mode>di2"
[(set (match_operand:DI 0 "s_register_operand" "=r") [(set (match_operand:DI 0 "s_register_operand" "=r")
(sign_extend:DI (match_operand:QHSI 1 "nonimmediate_operand" "rm")))] (sign_extend:DI (match_operand:QHSI 1 "<qhs_extenddi_op>"
"<qhs_extenddi_cstr>")))]
"TARGET_32BIT <qhs_sextenddi_cond>" "TARGET_32BIT <qhs_sextenddi_cond>"
"#" "#"
[(set_attr "length" "8") [(set_attr "length" "8")
......
...@@ -381,6 +381,10 @@ ...@@ -381,6 +381,10 @@
(define_mode_attr qhs_zextenddi_cond [(SI "") (HI "&& arm_arch6") (QI "")]) (define_mode_attr qhs_zextenddi_cond [(SI "") (HI "&& arm_arch6") (QI "")])
(define_mode_attr qhs_sextenddi_cond [(SI "") (HI "&& arm_arch6") (define_mode_attr qhs_sextenddi_cond [(SI "") (HI "&& arm_arch6")
(QI "&& arm_arch6")]) (QI "&& arm_arch6")])
(define_mode_attr qhs_extenddi_op [(SI "s_register_operand")
(HI "nonimmediate_operand")
(QI "nonimmediate_operand")])
(define_mode_attr qhs_extenddi_cstr [(SI "r") (HI "rm") (QI "rm")])
;;---------------------------------------------------------------------------- ;;----------------------------------------------------------------------------
;; Code attributes ;; Code attributes
......
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