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Commit c956e102 by Mark Shinwell Committed by Julian Brown
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arm.c (arm_mac_accumulator_is_mul_result): New. 

	gcc/
	* config/arm/arm.c (arm_mac_accumulator_is_mul_result): New.
	* config/arm/arm-protos.h (arm_mac_accumulator_is_mul_result): New.
	* config/arm/cortex-a8.md: New.
	* config/arm/cortex-a8-neon.md: New.
	* config/arm/neon-schedgen.ml: New.
	* config/arm/neon.md (vqh_mnem): New.
	(neon_type): New.
	(Is_float_mode): New.
	(Scalar_mul_8_16): New.
	(Is_d_reg): New.
	(V_mode_nunits): New.
	(All instruction patterns): Annotate with neon_type attribute
	values.
	* config/arm/arm.md: Include cortex-a8.md.
	(insn): Add smmla, umaal, smlald, smlsld, clz, mrs, msr and xtab
	values.
	Annotate instruction patterns accordingly.
	(generic_sched): Do not use generic scheduling for Cortex-A8.
	(generic_vfp): Do not use generic VFP scheduling for Cortex-A8.


Co-Authored-By: Julian Brown <julian@codesourcery.com>

From-SVN: r126953
parent 0c4d4efb
Showing with 67 additions and 5 deletions
gcc/ChangeLog
2007-07-26 Mark Shinwell <shinwell@codesourcery.com>
Julian Brown <julian@codesourcery.com>
* config/arm/arm.c (arm_mac_accumulator_is_mul_result): New.
* config/arm/arm-protos.h (arm_mac_accumulator_is_mul_result): New.
* config/arm/cortex-a8.md: New.
* config/arm/cortex-a8-neon.md: New.
* config/arm/neon-schedgen.ml: New.
* config/arm/neon.md (vqh_mnem): New.
(neon_type): New.
(Is_float_mode): New.
(Scalar_mul_8_16): New.
(Is_d_reg): New.
(V_mode_nunits): New.
(All instruction patterns): Annotate with neon_type attribute
values.
* config/arm/arm.md: Include cortex-a8.md.
(insn): Add smmla, umaal, smlald, smlsld, clz, mrs, msr and xtab
values.
Annotate instruction patterns accordingly.
(generic_sched): Do not use generic scheduling for Cortex-A8.
(generic_vfp): Do not use generic VFP scheduling for Cortex-A8.
2007-07-26 Daniel Jacobowitz <dan@codesourcery.com>
* fold-const.c (fold_read_from_constant_string): Use
......
gcc/config/arm/arm-protos.h
......@@ -94,6 +94,7 @@ extern int arm_no_early_store_addr_dep (rtx, rtx);
extern int arm_no_early_alu_shift_dep (rtx, rtx);
extern int arm_no_early_alu_shift_value_dep (rtx, rtx);
extern int arm_no_early_mul_dep (rtx, rtx);
extern int arm_mac_accumulator_is_mul_result (rtx, rtx);
extern int tls_mentioned_p (rtx);
extern int symbol_mentioned_p (rtx);
......
gcc/config/arm/arm.c
......@@ -18167,6 +18167,39 @@ arm_cxx_guard_type (void)
return TARGET_AAPCS_BASED ? integer_type_node : long_long_integer_type_node;
}
/* Return non-zero if the consumer (a multiply-accumulate instruction)
has an accumulator dependency on the result of the producer (a
multiplication instruction) and no other dependency on that result. */
int
arm_mac_accumulator_is_mul_result (rtx producer, rtx consumer)
{
rtx mul = PATTERN (producer);
rtx mac = PATTERN (consumer);
rtx mul_result;
rtx mac_op0, mac_op1, mac_acc;
if (GET_CODE (mul) == COND_EXEC)
mul = COND_EXEC_CODE (mul);
if (GET_CODE (mac) == COND_EXEC)
mac = COND_EXEC_CODE (mac);
/* Check that mul is of the form (set (...) (mult ...))
and mla is of the form (set (...) (plus (mult ...) (...))). */
if ((GET_CODE (mul) != SET || GET_CODE (XEXP (mul, 1)) != MULT)
|| (GET_CODE (mac) != SET || GET_CODE (XEXP (mac, 1)) != PLUS
|| GET_CODE (XEXP (XEXP (mac, 1), 0)) != MULT))
return 0;
mul_result = XEXP (mul, 0);
mac_op0 = XEXP (XEXP (XEXP (mac, 1), 0), 0);
mac_op1 = XEXP (XEXP (XEXP (mac, 1), 0), 1);
mac_acc = XEXP (XEXP (mac, 1), 1);
return (reg_overlap_mentioned_p (mul_result, mac_acc)
&& !reg_overlap_mentioned_p (mul_result, mac_op0)
&& !reg_overlap_mentioned_p (mul_result, mac_op1));
}
/* The EABI says test the least significant bit of a guard variable. */
......
gcc/config/arm/arm.md
......@@ -184,7 +184,7 @@
;; scheduling information.
(define_attr "insn"
"smulxy,smlaxy,smlalxy,smulwy,smlawx,mul,muls,mla,mlas,umull,umulls,umlal,umlals,smull,smulls,smlal,smlals,smlawy,smuad,smuadx,smlad,smladx,smusd,smusdx,smlsd,smlsdx,smmul,smmulr,other"
"mov,mvn,smulxy,smlaxy,smlalxy,smulwy,smlawx,mul,muls,mla,mlas,umull,umulls,umlal,umlals,smull,smulls,smlal,smlals,smlawy,smuad,smuadx,smlad,smladx,smusd,smusdx,smlsd,smlsdx,smmul,smmulr,smmla,umaal,smlald,smlsld,clz,mrs,msr,xtab,other"
(const_string "other"))
; TYPE attribute is used to detect floating point instructions which, if
......@@ -235,8 +235,9 @@
; mav_farith Floating point arithmetic (4 cycle)
; mav_dmult Double multiplies (7 cycle)
;
(define_attr "type"
"alu,alu_shift,alu_shift_reg,mult,block,float,fdivx,fdivd,fdivs,fmul,ffmul,farith,ffarith,f_flag,float_em,f_load,f_store,f_loads,f_loadd,f_stores,f_stored,f_mem_r,r_mem_f,f_2_r,r_2_f,f_cvt,branch,call,load_byte,load1,load2,load3,load4,store1,store2,store3,store4,mav_farith,mav_dmult"
"alu,alu_shift,alu_shift_reg,mult,block,float,fdivx,fdivd,fdivs,fmul,fmuls,fmuld,fmacs,fmacd,ffmul,farith,ffarith,f_flag,float_em,f_load,f_store,f_loads,f_loadd,f_stores,f_stored,f_mem_r,r_mem_f,f_2_r,r_2_f,f_cvt,branch,call,load_byte,load1,load2,load3,load4,store1,store2,store3,store4,mav_farith,mav_dmult"
(if_then_else
(eq_attr "insn" "smulxy,smlaxy,smlalxy,smulwy,smlawx,mul,muls,mla,mlas,umull,umulls,umlal,umlals,smull,smulls,smlal,smlals")
(const_string "mult")
......@@ -332,14 +333,14 @@
(define_attr "generic_sched" "yes,no"
(const (if_then_else
(eq_attr "tune" "arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs")
(eq_attr "tune" "arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa8")
(const_string "no")
(const_string "yes"))))
(define_attr "generic_vfp" "yes,no"
(const (if_then_else
(and (eq_attr "fpu" "vfp")
(eq_attr "tune" "!arm1020e,arm1022e"))
(eq_attr "tune" "!arm1020e,arm1022e,cortexa8"))
(const_string "yes")
(const_string "no"))))
......@@ -348,6 +349,7 @@
(include "arm1020e.md")
(include "arm1026ejs.md")
(include "arm1136jfs.md")
(include "cortex-a8.md")
;;---------------------------------------------------------------------------
......@@ -3869,6 +3871,7 @@
"TARGET_INT_SIMD"
"uxtab%?\\t%0, %2, %1"
[(set_attr "predicable" "yes")
(set_attr "insn" "xtab")
(set_attr "type" "alu_shift")]
)
......@@ -4242,6 +4245,7 @@
"TARGET_INT_SIMD"
"sxtab%?\\t%0, %2, %1"
[(set_attr "type" "alu_shift")
(set_attr "insn" "xtab")
(set_attr "predicable" "yes")]
)
......@@ -10772,7 +10776,8 @@
(clz:SI (match_operand:SI 1 "s_register_operand" "r")))]
"TARGET_32BIT && arm_arch5"
"clz%?\\t%0, %1"
[(set_attr "predicable" "yes")])
[(set_attr "predicable" "yes")
(set_attr "insn" "clz")])
(define_expand "ffssi2"
[(set (match_operand:SI 0 "s_register_operand" "")
......
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