Skip to content

R
riscv-gcc-1
Commit c93c5160 by Richard Sandiford Committed by Richard Sandiford
Options

invoke.texi (-mcode-readable): Document. 

gcc/
2007-08-08  Richard Sandiford  <richard@codesourcery.com>
	    Sandra Loosemore  <sandra@codesourcery.com>
	    Chao-ying Fu  <fu@mips.com>
	    Nigel Stephens  <nigel@mips.com>
	    David Ung  <davidu@mips.com>

	* doc/invoke.texi (-mcode-readable): Document.
	* config/mips/mips.opt (mcode-readable): New option.
	* config/mips/mips-protos.h (SYMBOL_32_HIGH): New symbol type.
	* config/mips/mips.h (mips_code_readable_setting): New enum.
	(mips_code_readable): Declare.
	(TARGET_MIPS16_TEXT_LOADS, TARGET_MIPS16_PCREL_LOADS): New macros.
	(TARGET_MIPS16_SHORT_JUMP_TABLES): New macro.
	(JUMP_TABLES_IN_TEXT_SECTION): Use it.
	(CASE_VECTOR_MODE, CASE_VECTOR_PC_RELATIVE): Likewise.  Remove
	boiler-plate comments.
	(ASM_OUTPUT_ADDR_DIFF_ELT): Use TARGET_MIPS16_SHORT_JUMP_TABLES.
	* config/mips/mips.c (mips_code_readable): New variable.
	(mips_classify_symbol): Only return SYMBOL_PC_RELATIVE for
	MIPS16 labels if TARGET_MIPS16_SHORT_JUMP_TABLES.  Use both the
	context and -mcode-readable setting to restrict the use of
	SYMBOL_PC_RELATIVE for MIPS16 constant pool references.
	Only return TARGET_FORCE_TO_MEM if PC-relative loads are allowed.
	(mips_symbolic_constant_p): Handle SYMBOL_32_HIGH.
	(mips_blocks_for_constant_p): Only return false for
	TARGET_MIPS16_PCREL_LOADS.
	(mips_symbol_insns_1): Treat HIGHs as 2 extended instructions
	for MIPS16.  Handle SYMBOL_32_HIGH.
	(mips_const_insns): Allow HIGHs for MIPS16 too.
	(mips_unspec_address_offset): New function, split out from...
	(mips_unspec_address): ...here.
	(mips_output_move): Handle MIPS16 HIGH moves.  Use "li" to load
	16-bit symbolic constants.  Assert approropiate conditions for
	using the "la" and "dla" macros.
	(mips_handle_option): Handle -mcode-readable=.
	(override_options): Use %hi/%lo relocations for TARGET_MIPS16 too.
	Set up mips_lo_relocs[SYMBOL_32_HIGH].
	(mips_strip_unspec_address): New function, split out from...
	(print_operand_reloc): ...here.
	(print_operand): Pass constants through mips_strip_unspec_address.
	(print_operand_address): Likewise.
	(mips_output_mi_thunk): Remove guard of mips16_lay_out_constants.
	(mips_select_rtx_section): Remove MIPS16 handling.
	(mips16_gp_pseudo_reg): Check currently_expanding_to_rtl.
	(mips16_rewrite_pool_refs): Wrap the labels in an address UNSPEC.
	(mips16_lay_out_constants): Do nothing unless
	TARGET_MIPS16_PCREL_LOADS.
	(mips_avoid_hazards): Remove guard of mips16_lay_out_constants.
	* config/mips/mips.md: Split HIGHs for MIPS16.
	(tablejump): Use TARGET_MIPS16_SHORT_JUMP_TABLES.

gcc/testsuite/
	* gcc.target/mips/code-readable-1.c: New test.
	* gcc.target/mips/code-readable-2.c: Likewise.
	* gcc.target/mips/code-readable-3.c: Likewise.

Co-Authored-By: Chao-ying Fu <fu@mips.com>
Co-Authored-By: David Ung <davidu@mips.com>
Co-Authored-By: Nigel Stephens <nigel@mips.com>
Co-Authored-By: Sandra Loosemore <sandra@codesourcery.com>

From-SVN: r127300
parent 51e7252a
Showing with 354 additions and 65 deletions
gcc/ChangeLog
2007-08-08 Richard Sandiford <richard@codesourcery.com>
Sandra Loosemore <sandra@codesourcery.com>
Chao-ying Fu <fu@mips.com>
Nigel Stephens <nigel@mips.com>
David Ung <davidu@mips.com>
* doc/invoke.texi (-mcode-readable): Document.
* config/mips/mips.opt (mcode-readable): New option.
* config/mips/mips-protos.h (SYMBOL_32_HIGH): New symbol type.
* config/mips/mips.h (mips_code_readable_setting): New enum.
(mips_code_readable): Declare.
(TARGET_MIPS16_TEXT_LOADS, TARGET_MIPS16_PCREL_LOADS): New macros.
(TARGET_MIPS16_SHORT_JUMP_TABLES): New macro.
(JUMP_TABLES_IN_TEXT_SECTION): Use it.
(CASE_VECTOR_MODE, CASE_VECTOR_PC_RELATIVE): Likewise. Remove
boiler-plate comments.
(ASM_OUTPUT_ADDR_DIFF_ELT): Use TARGET_MIPS16_SHORT_JUMP_TABLES.
* config/mips/mips.c (mips_code_readable): New variable.
(mips_classify_symbol): Only return SYMBOL_PC_RELATIVE for
MIPS16 labels if TARGET_MIPS16_SHORT_JUMP_TABLES. Use both the
context and -mcode-readable setting to restrict the use of
SYMBOL_PC_RELATIVE for MIPS16 constant pool references.
Only return TARGET_FORCE_TO_MEM if PC-relative loads are allowed.
(mips_symbolic_constant_p): Handle SYMBOL_32_HIGH.
(mips_blocks_for_constant_p): Only return false for
TARGET_MIPS16_PCREL_LOADS.
(mips_symbol_insns_1): Treat HIGHs as 2 extended instructions
for MIPS16. Handle SYMBOL_32_HIGH.
(mips_const_insns): Allow HIGHs for MIPS16 too.
(mips_unspec_address_offset): New function, split out from...
(mips_unspec_address): ...here.
(mips_output_move): Handle MIPS16 HIGH moves. Use "li" to load
16-bit symbolic constants. Assert approropiate conditions for
using the "la" and "dla" macros.
(mips_handle_option): Handle -mcode-readable=.
(override_options): Use %hi/%lo relocations for TARGET_MIPS16 too.
Set up mips_lo_relocs[SYMBOL_32_HIGH].
(mips_strip_unspec_address): New function, split out from...
(print_operand_reloc): ...here.
(print_operand): Pass constants through mips_strip_unspec_address.
(print_operand_address): Likewise.
(mips_output_mi_thunk): Remove guard of mips16_lay_out_constants.
(mips_select_rtx_section): Remove MIPS16 handling.
(mips16_gp_pseudo_reg): Check currently_expanding_to_rtl.
(mips16_rewrite_pool_refs): Wrap the labels in an address UNSPEC.
(mips16_lay_out_constants): Do nothing unless
TARGET_MIPS16_PCREL_LOADS.
(mips_avoid_hazards): Remove guard of mips16_lay_out_constants.
* config/mips/mips.md: Split HIGHs for MIPS16.
(tablejump): Use TARGET_MIPS16_SHORT_JUMP_TABLES.
2007-08-08 Richard Sandiford <richard@codesourcery.com>
* config/mips/mips-protos.h (mips_emit_move): Declare.
* config/mips/mips.c (mips_emit_move): New function.
......
gcc/config/mips/mips-protos.h
......@@ -93,6 +93,9 @@ enum mips_symbol_context {
UNSPEC wrappers around SYMBOL_TLS, corresponding to the
thread-local storage relocation operators.
SYMBOL_32_HIGH
For a 32-bit symbolic address X, this is the value of %hi(X).
SYMBOL_64_HIGH
For a 64-bit symbolic address X, this is the value of
(%highest(X) << 16) + %higher(X).
......@@ -125,6 +128,7 @@ enum mips_symbol_type {
SYMBOL_DTPREL,
SYMBOL_GOTTPREL,
SYMBOL_TPREL,
SYMBOL_32_HIGH,
SYMBOL_64_HIGH,
SYMBOL_64_MID,
SYMBOL_64_LOW,
......
gcc/config/mips/mips.h
......@@ -114,6 +114,13 @@ struct mips_cpu_info {
int isa;
};
/* Enumerates the setting of the -mcode-readable option. */
enum mips_code_readable_setting {
CODE_READABLE_NO,
CODE_READABLE_PCREL,
CODE_READABLE_YES
};
#ifndef USED_FOR_TARGET
extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
extern const char *current_function_file; /* filename current function is in */
......@@ -138,6 +145,7 @@ extern const struct mips_cpu_info mips_cpu_info_table[];
extern const struct mips_cpu_info *mips_arch_info;
extern const struct mips_cpu_info *mips_tune_info;
extern const struct mips_rtx_cost_data *mips_cost;
extern enum mips_code_readable_setting mips_code_readable;
#endif
/* Macros to silence warnings about numbers being signed in traditional
......@@ -214,6 +222,16 @@ extern const struct mips_rtx_cost_data *mips_cost;
/* Generate mips16e register save/restore sequences. */
#define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
/* True if we're generating a form of MIPS16 code in which general
text loads are allowed. */
#define TARGET_MIPS16_TEXT_LOADS \
(TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
/* True if we're generating a form of MIPS16 code in which PC-relative
loads are allowed. */
#define TARGET_MIPS16_PCREL_LOADS \
(TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
/* Generic ISA defines. */
#define ISA_MIPS1 (mips_isa == 1)
#define ISA_MIPS2 (mips_isa == 2)
......@@ -2270,17 +2288,18 @@ typedef struct mips_args {
#define SYMBOL_REF_LONG_CALL_P(X) \
((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
/* Specify the machine mode that this machine uses
for the index in the tablejump instruction.
??? Using HImode in mips16 mode can cause overflow. */
#define CASE_VECTOR_MODE \
(TARGET_MIPS16 ? HImode : ptr_mode)
/* True if we're generating a form of MIPS16 code in which jump tables
are stored in the text section and encoded as 16-bit PC-relative
offsets. This is only possible when general text loads are allowed,
since the table access itself will be an "lh" instruction. */
/* ??? 16-bit offsets can overflow in large functions. */
#define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
/* Define as C expression which evaluates to nonzero if the tablejump
instruction expects the table to contain offsets from the address of the
table.
Do not define this if the table should contain absolute addresses. */
#define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
#define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
#define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? HImode : ptr_mode)
#define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
/* Define this as 1 if `char' should by default be signed; else as 0. */
#ifndef DEFAULT_SIGNED_CHAR
......@@ -2650,7 +2669,7 @@ while (0)
#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
do { \
if (TARGET_MIPS16) \
if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
else if (TARGET_GPWORD) \
......@@ -2673,10 +2692,6 @@ do { \
LOCAL_LABEL_PREFIX, VALUE); \
} while (0)
/* When generating MIPS16 code, we want the jump table to be in the text
section so that we can load its address using a PC-relative addition. */
#define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16
/* This is how to output an assembler line
that says to advance the location counter
to a multiple of 2**LOG bytes. */
......
gcc/config/mips/mips.md
......@@ -3181,6 +3181,22 @@
}
[(set_attr "length" "24")])
;; Split HIGHs into:
;;
;; li op0,%hi(sym)
;; sll op0,16
;;
;; on MIPS16 targets.
(define_split
[(set (match_operand:SI 0 "register_operand" "=d")
(high:SI (match_operand:SI 1 "absolute_symbolic_operand" "")))]
"TARGET_MIPS16 && reload_completed"
[(set (match_dup 0) (match_dup 2))
(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 16)))]
{
operands[2] = mips_unspec_address (operands[1], SYMBOL_32_HIGH);
})
;; Insns to fetch a symbol from a big GOT.
(define_insn_and_split "*xgot_hi<mode>"
......@@ -5050,7 +5066,7 @@
(use (label_ref (match_operand 1 "")))]
""
{
if (TARGET_MIPS16)
if (TARGET_MIPS16_SHORT_JUMP_TABLES)
operands[0] = expand_binop (Pmode, add_optab,
convert_to_mode (Pmode, operands[0], false),
gen_rtx_LABEL_REF (Pmode, operands[1]),
......
gcc/config/mips/mips.opt
......@@ -228,6 +228,10 @@ msym32
Target Report Var(TARGET_SYM32)
Assume all symbols have 32-bit values
mcode-readable=
Target RejectNegative Joined
-mcode-readable=SETTING Specify when instructions are allowed to access code
mtune=
Target RejectNegative Joined Var(mips_tune_string)
-mtune=PROCESSOR Optimize the output for PROCESSOR
......
gcc/doc/invoke.texi
......@@ -628,6 +628,7 @@ Objective-C and Objective-C++ Dialects}.
-mlong64 -mlong32 -msym32 -mno-sym32 @gol
-G@var{num} -membedded-data -mno-embedded-data @gol
-muninit-const-in-rodata -mno-uninit-const-in-rodata @gol
-mcode-readable=@var{setting} @gol
-msplit-addresses -mno-split-addresses @gol
-mexplicit-relocs -mno-explicit-relocs @gol
-mcheck-zero-division -mno-check-zero-division @gol
......@@ -11779,6 +11780,31 @@ when executing, and thus may be preferred for some embedded systems.
Put uninitialized @code{const} variables in the read-only data section.
This option is only meaningful in conjunction with @option{-membedded-data}.
@item -mcode-readable=@var{setting}
@opindex mcode-readable
Specify whether GCC may generate code that reads from executable sections.
There are three possible settings:
@table @gcctabopt
@item -mcode-readable=yes
Instructions may freely access executable sections. This is the
default setting.
@item -mcode-readable=pcrel
MIPS16 PC-relative load instructions can access executable sections,
but other instructions must not do so. This option is useful on 4KSc
and 4KSd processors when the code TLBs have the Read Inhibit bit set.
It is also useful on processors that can be configured to have a dual
instruction/data SRAM interface and that, like the M4K, automatically
redirect PC-relative loads to the instruction RAM.
@item -mcode-readable=no
Instructions must not access executable sections. This option can be
useful on targets that are configured to have a dual instruction/data
SRAM interface but that (unlike the M4K) do not automatically redirect
PC-relative loads to the instruction RAM.
@end table
@item -msplit-addresses
@itemx -mno-split-addresses
@opindex msplit-addresses
......
gcc/testsuite/ChangeLog
2007-08-08 Richard Sandiford <richard@codesourcery.com>
* gcc.target/mips/code-readable-1.c: New test.
* gcc.target/mips/code-readable-2.c: Likewise.
* gcc.target/mips/code-readable-3.c: Likewise.
2007-08-08 Vladimir Yanovsky <yanov@il.ibm.com>
Revital Eres <eres@il.ibm.com>
gcc/testsuite/gcc.target/mips/code-readable-1.c 0 → 100644
/* { dg-mips-options "-mips16 -mcode-readable=yes -mgp32" } */
int
foo (int i)
{
switch (i)
{
case 1: return 40;
case 2: return 11;
case 3: return 29;
case 4: return 10;
case 5: return 12;
case 6: return 35;
case 7: return 23;
default: return 0;
}
}
extern int k[];
int *
bar (void)
{
return k;
}
/* { dg-final { scan-assembler "\tla\t" } } */
/* { dg-final { scan-assembler "\t\.half\t" } } */
/* { dg-final { scan-assembler-not "%hi\\(\[^)\]*L" } } */
/* { dg-final { scan-assembler-not "%lo\\(\[^)\]*L" } } */
/* { dg-final { scan-assembler "\t\.word\tk\n" } } */
/* { dg-final { scan-assembler-not "%hi\\(k\\)" } } */
/* { dg-final { scan-assembler-not "%lo\\(k\\)" } } */
gcc/testsuite/gcc.target/mips/code-readable-2.c 0 → 100644
/* { dg-mips-options "-mips16 -mcode-readable=pcrel -mgp32" } */
int
foo (int i)
{
switch (i)
{
case 1: return 40;
case 2: return 11;
case 3: return 29;
case 4: return 10;
case 5: return 12;
case 6: return 35;
case 7: return 23;
default: return 0;
}
}
extern int k[];
int *
bar (void)
{
return k;
}
/* { dg-final { scan-assembler-not "\tla\t" } } */
/* { dg-final { scan-assembler-not "\t\.half\t" } } */
/* { dg-final { scan-assembler "%hi\\(\[^)\]*L" } } */
/* { dg-final { scan-assembler "%lo\\(\[^)\]*L" } } */
/* { dg-final { scan-assembler "\t\.word\tk\n" } } */
/* { dg-final { scan-assembler-not "%hi\\(k\\)" } } */
/* { dg-final { scan-assembler-not "%lo\\(k\\)" } } */
gcc/testsuite/gcc.target/mips/code-readable-3.c 0 → 100644
/* { dg-mips-options "-mips16 -mcode-readable=no -mgp32" } */
int
foo (int i)
{
switch (i)
{
case 1: return 40;
case 2: return 11;
case 3: return 29;
case 4: return 10;
case 5: return 12;
case 6: return 35;
case 7: return 23;
default: return 0;
}
}
extern int k[];
int *
bar (void)
{
return k;
}
/* { dg-final { scan-assembler-not "\tla\t" } } */
/* { dg-final { scan-assembler-not "\t\.half\t" } } */
/* { dg-final { scan-assembler "%hi\\(\[^)\]*L" } } */
/* { dg-final { scan-assembler "%lo\\(\[^)\]*L" } } */
/* { dg-final { scan-assembler-not "\t\.word\tk\n" } } */
/* { dg-final { scan-assembler "%hi\\(k\\)" } } */
/* { dg-final { scan-assembler "%lo\\(k\\)" } } */
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment