aarch64.md (*mov<mode>_aarch64): Add variants for scalar load/store operations using B/H registers.

	* config/aarch64/aarch64.md (*mov<mode>_aarch64): Add variants for scalar
	load/store operations using B/H registers.
	(*zero_extend<SHORT:mode><GPI:mode>2_aarch64): Likewise.

From-SVN: r197342

gcc/ChangeLog

 2013-04-02  Sofiane Naci  <sofiane.naci@arm.com>
 
+	* config/aarch64/aarch64.md (*mov<mode>_aarch64): Add variants for scalar
+	load/store operations using B/H registers.
+	(*zero_extend<SHORT:mode><GPI:mode>2_aarch64): Likewise.
+
+2013-04-02  Sofiane Naci  <sofiane.naci@arm.com>
+
 	* config/aarch64/aarch64.md (*mov<mode>_aarch64): Add alternatives for
 	scalar move.
 	* config/aarch64/aarch64.c

gcc/config/aarch64/aarch64.md

@@ -763,8 +763,8 @@
 )
 
 (define_insn "*mov<mode>_aarch64"
-  [(set (match_operand:SHORT 0 "nonimmediate_operand" "=r,r,   *w,r, m, r,*w,*w")
-        (match_operand:SHORT 1 "general_operand"      " r,M,D<hq>,m,rZ,*w, r,*w"))]
+  [(set (match_operand:SHORT 0 "nonimmediate_operand" "=r,r,   *w,r,*w, m, m, r,*w,*w")
+        (match_operand:SHORT 1 "general_operand"      " r,M,D<hq>,m, m,rZ,*w,*w, r,*w"))]
   "(register_operand (operands[0], <MODE>mode)
     || aarch64_reg_or_zero (operands[1], <MODE>mode))"
   "@
@@ -772,12 +772,14 @@
    mov\\t%w0, %1
    movi\\t%0.<Vallxd>, %1
    ldr<size>\\t%w0, %1
+   ldr\\t%<size>0, %1
    str<size>\\t%w1, %0
+   str\\t%<size>1, %0
    umov\\t%w0, %1.<v>[0]
    dup\\t%0.<Vallxd>, %w1
    dup\\t%0, %1.<v>[0]"
-  [(set_attr "v8type" "move,alu,alu,load1,store1,*,*,*")
-   (set_attr "simd_type" "*,*,simd_move_imm,*,*,simd_movgp,simd_dupgp,simd_dup")
+  [(set_attr "v8type" "move,alu,alu,load1,load1,store1,store1,*,*,*")
+   (set_attr "simd_type" "*,*,simd_move_imm,*,*,*,*,simd_movgp,simd_dupgp,simd_dup")
    (set_attr "mode" "<MODE>")
    (set_attr "simd_mode" "<MODE>")]
 )
@@ -1151,13 +1153,14 @@
 )
 
 (define_insn "*zero_extend<SHORT:mode><GPI:mode>2_aarch64"
-  [(set (match_operand:GPI 0 "register_operand" "=r,r")
-        (zero_extend:GPI (match_operand:SHORT 1 "nonimmediate_operand" "r,m")))]
+  [(set (match_operand:GPI 0 "register_operand" "=r,r,*w")
+        (zero_extend:GPI (match_operand:SHORT 1 "nonimmediate_operand" "r,m,m")))]
   ""
   "@
    uxt<SHORT:size>\t%<GPI:w>0, %w1
-   ldr<SHORT:size>\t%w0, %1"
-  [(set_attr "v8type" "extend,load1")
+   ldr<SHORT:size>\t%w0, %1
+   ldr\t%<SHORT:size>0, %1"
+  [(set_attr "v8type" "extend,load1,load1")
    (set_attr "mode" "<GPI:MODE>")]
 )