arm-modes.def: Add new condition code mode CC_V to represent the overflow bit.

2016-08-24  Michael Collison <michael.collison@linaro.org>
	    Michael Collison <michael.collison@arm.com>

	* config/arm/arm-modes.def: Add new condition code mode CC_V
	to represent the overflow bit.
	* config/arm/arm.c (maybe_get_arm_condition_code):
	Add support for CC_Vmode.
	(arm_gen_unlikely_cbranch): New function to generate common
	rtl conditional branches for overflow patterns.
	* config/arm/arm-protos.h: Add prototype for
	arm_gen_unlikely_cbranch.
	* config/arm/arm.md (addv<mode>4, add<mode>3_compareV,
	addsi3_compareV_upper): New patterns to support signed
	builtin overflow add operations.
	(uaddv<mode>4, add<mode>3_compareC, addsi3_compareV_upper):
	New patterns to support unsigned builtin add overflow operations.
	(subv<mode>4, sub<mode>3_compare1): New patterns to support signed
	builtin overflow subtract operations,
	(usubv<mode>4): New patterns to support unsigned builtin subtract
	overflow operations.
	(negvsi3, negvdi3, negdi2_compare, negsi2_carryin_compare): New patterns
	to support builtin overflow negate operations.
	* gcc.target/arm/builtin_saddl.c: New testcase.
	* gcc.target/arm/builtin_saddll.c: New testcase.
	* gcc.target/arm/builtin_uaddl.c: New testcase.
	* gcc.target/arm/builtin_uaddll.c: New testcase.
	* gcc.target/arm/builtin_ssubl.c: New testcase.
	* gcc.target/arm/builtin_ssubll.c: New testcase.
	* gcc.target/arm/builtin_usubl.c: New testcase.
	* gcc.target/arm/builtin_usubll.c: New testcase.


Co-Authored-By: Michael Collison <michael.collison@arm.com>

From-SVN: r239739

gcc/ChangeLog

+2016-08-24  Michael Collison <michael.collison@linaro.org>
+	    Michael Collison <michael.collison@arm.com>
+
+	* config/arm/arm-modes.def: Add new condition code mode CC_V
+	to represent the overflow bit.
+	* config/arm/arm.c (maybe_get_arm_condition_code):
+	Add support for CC_Vmode.
+	(arm_gen_unlikely_cbranch): New function to generate common
+	rtl conditional branches for overflow patterns.
+	* config/arm/arm-protos.h: Add prototype for
+	arm_gen_unlikely_cbranch.
+	* config/arm/arm.md (addv<mode>4, add<mode>3_compareV,
+	addsi3_compareV_upper): New patterns to support signed
+	builtin overflow add operations.
+	(uaddv<mode>4, add<mode>3_compareC, addsi3_compareV_upper):
+	New patterns to support unsigned builtin add overflow operations.
+	(subv<mode>4, sub<mode>3_compare1): New patterns to support signed
+	builtin overflow subtract operations,
+	(usubv<mode>4): New patterns to support unsigned builtin subtract
+	overflow operations.
+	(negvsi3, negvdi3, negdi2_compare, negsi2_carryin_compare): New patterns
+	to support builtin overflow negate operations.
+
 2016-08-24  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 
 	Revert

gcc/config/arm/arm-modes.def

@@ -59,6 +59,7 @@ CC_MODE (CC_DGEU);
 CC_MODE (CC_DGTU);
 CC_MODE (CC_C);
 CC_MODE (CC_N);
+CC_MODE (CC_V);
 
 /* Vector modes.  */
 VECTOR_MODES (INT, 4);        /*            V4QI V2HI */

gcc/config/arm/arm-protos.h

@@ -54,6 +54,8 @@ extern rtx arm_simd_vect_par_cnst_half (machine_mode mode, bool high);
 extern bool arm_simd_check_vect_par_cnst_half_p (rtx op, machine_mode mode,
 						 bool high);
 #ifdef RTX_CODE
+extern void arm_gen_unlikely_cbranch (enum rtx_code, machine_mode cc_mode,
+				      rtx label_ref);
 extern bool arm_vector_mode_supported_p (machine_mode);
 extern bool arm_small_register_classes_for_mode_p (machine_mode);
 extern int arm_hard_regno_mode_ok (unsigned int, machine_mode);

gcc/config/arm/arm.c

@@ -22992,6 +22992,8 @@ maybe_get_arm_condition_code (rtx comparison)
 	{
 	case LTU: return ARM_CS;
 	case GEU: return ARM_CC;
+	case NE: return ARM_CS;
+	case EQ: return ARM_CC;
 	default: return ARM_NV;
 	}
 
@@ -23017,6 +23019,14 @@ maybe_get_arm_condition_code (rtx comparison)
 	default: return ARM_NV;
 	}
 
+    case CC_Vmode:
+      switch (comp_code)
+	{
+	case NE: return ARM_VS;
+	case EQ: return ARM_VC;
+	default: return ARM_NV;
+	}
+
     case CCmode:
       switch (comp_code)
 	{
@@ -30575,4 +30585,23 @@ arm_can_output_mi_thunk (const_tree, HOST_WIDE_INT, HOST_WIDE_INT vcall_offset,
   return true;
 }
 
+/* Generate RTL for a conditional branch with rtx comparison CODE in
+   mode CC_MODE. The destination of the unlikely conditional branch
+   is LABEL_REF.  */
+
+void
+arm_gen_unlikely_cbranch (enum rtx_code code, machine_mode cc_mode,
+			  rtx label_ref)
+{
+  rtx x;
+  x = gen_rtx_fmt_ee (code, VOIDmode,
+		      gen_rtx_REG (cc_mode, CC_REGNUM),
+		      const0_rtx);
+
+  x = gen_rtx_IF_THEN_ELSE (VOIDmode, x,
+			    gen_rtx_LABEL_REF (VOIDmode, label_ref),
+			    pc_rtx);
+  emit_unlikely_jump (gen_rtx_SET (pc_rtx, x));
+}
+
 #include "gt-arm.h"

gcc/testsuite/ChangeLog

+2016-08-24  Michael Collison <michael.collison@linaro.org>
+	    Michael Collison <michael.collison@arm.com>
+
+	* gcc.target/arm/builtin_saddl.c: New testcase.
+	* gcc.target/arm/builtin_saddll.c: New testcase.
+	* gcc.target/arm/builtin_uaddl.c: New testcase.
+	* gcc.target/arm/builtin_uaddll.c: New testcase.
+	* gcc.target/arm/builtin_ssubl.c: New testcase.
+	* gcc.target/arm/builtin_ssubll.c: New testcase.
+	* gcc.target/arm/builtin_usubl.c: New testcase.
+	* gcc.target/arm/builtin_usubll.c: New testcase.
+
 2016-08-24  Uros Bizjak  <ubizjak@gmail.com>
 
 	PR target/77270

gcc/testsuite/gcc.target/arm/builtin_saddl.c

+/* { dg-do compile } */
+/* { dg-options "-O2" }  */
+/* { dg-require-effective-target arm32 } */
+extern void overflow_handler ();
+
+long overflow_add (long x, long y)
+{
+  long r;
+
+  int ovr = __builtin_saddl_overflow (x, y, &r);
+  if (ovr)
+    overflow_handler ();
+
+  return r;
+}
+
+/* { dg-final { scan-assembler "adds" } } */

gcc/testsuite/gcc.target/arm/builtin_saddll.c

+/* { dg-do compile } */
+/* { dg-options "-O2" }  */
+/* { dg-require-effective-target arm32 } */
+extern void overflow_handler ();
+
+long long overflow_add (long long x, long long y)
+{
+  long long r;
+
+  int ovr = __builtin_saddll_overflow (x, y, &r);
+  if (ovr)
+    overflow_handler ();
+
+  return r;
+}
+
+/* { dg-final { scan-assembler "adds" } } */
+/* { dg-final { scan-assembler "adcs" } } */

gcc/testsuite/gcc.target/arm/builtin_ssubl.c

+/* { dg-do compile } */
+/* { dg-options "-O2" }  */
+/* { dg-require-effective-target arm32 } */
+extern void overflow_handler ();
+
+long overflow_sub (long x, long y)
+{
+  long r;
+
+  int ovr = __builtin_ssubl_overflow (x, y, &r);
+  if (ovr)
+    overflow_handler ();
+
+  return r;
+}
+
+/* { dg-final { scan-assembler "subs" } } */

gcc/testsuite/gcc.target/arm/builtin_ssubll.c

+/* { dg-do compile } */
+/* { dg-options "-O2" }  */
+/* { dg-require-effective-target arm32 } */
+extern void overflow_handler ();
+
+long long overflow_sub (long long x, long long y)
+{
+  long long r;
+
+  int ovr = __builtin_ssubll_overflow (x, y, &r);
+  if (ovr)
+    overflow_handler ();
+
+  return r;
+}
+
+/* { dg-final { scan-assembler "subs" } } */
+/* { dg-final { scan-assembler "sbcs" } } */

gcc/testsuite/gcc.target/arm/builtin_uaddl.c

+/* { dg-do compile } */
+/* { dg-options "-O2" }  */
+/* { dg-require-effective-target arm32 } */
+extern void overflow_handler ();
+
+unsigned long overflow_add (unsigned long x, unsigned long y)
+{
+  unsigned long r;
+
+  int ovr = __builtin_uaddl_overflow (x, y, &r);
+  if (ovr)
+    overflow_handler ();
+
+  return r;
+}
+
+/* { dg-final { scan-assembler "adds" } } */

gcc/testsuite/gcc.target/arm/builtin_uaddll.c

+/* { dg-do compile } */
+/* { dg-options "-O2" }  */
+/* { dg-require-effective-target arm32 } */
+extern void overflow_handler ();
+
+unsigned long long overflow_add (unsigned long long x, unsigned long long y)
+{
+  unsigned long long r;
+
+  int ovr = __builtin_uaddll_overflow (x, y, &r);
+  if (ovr)
+    overflow_handler ();
+
+  return r;
+}
+
+/* { dg-final { scan-assembler "adds" } } */
+/* { dg-final { scan-assembler "adcs" } } */

gcc/testsuite/gcc.target/arm/builtin_usubl.c

+/* { dg-do compile } */
+/* { dg-options "-O2" }  */
+/* { dg-require-effective-target arm32 } */
+extern void overflow_handler ();
+
+unsigned long overflow_sub (unsigned long x, unsigned long y)
+{
+  unsigned long r;
+
+  int ovr = __builtin_usubl_overflow (x, y, &r);
+  if (ovr)
+    overflow_handler ();
+
+  return r;
+}
+
+/* { dg-final { scan-assembler "subs" } } */

gcc/testsuite/gcc.target/arm/builtin_usubll.c

+/* { dg-do compile } */
+/* { dg-options "-O2" }  */
+/* { dg-require-effective-target arm32 } */
+extern void overflow_handler ();
+
+unsigned long long overflow_sub (unsigned long long x, unsigned long long y)
+{
+  unsigned long long r;
+
+  int ovr = __builtin_usubll_overflow (x, y, &r);
+  if (ovr)
+    overflow_handler ();
+
+  return r;
+}
+
+/* { dg-final { scan-assembler "subs" } } */
+/* { dg-final { scan-assembler "sbcs" } } */