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riscv-gcc-1
Commit c75d6010 by James A. Morrison Committed by Eric Botcazou
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re PR target/18230 (SPARC VIS instructions are not generated by GCC) 

	PR target/18230
	* doc/md.texi (SPARC constraints): Document 'Y' constraint.
	* config/sparc/sparc-modes.def: Add vector modes of 4 and 8 bytes.
	* config/sparc/sparc.c (sparc_vector_mode_supported_p): New function.
	(TARGET_VECTOR_MODE_SUPPORTED_P): Set to sparc_vector_mode_supported_p.
	(fp_zero_operand): Accept MODE_VECTOR_INT modes.
	(input_operand): Accept CONST_VECTOR with MODE_VECTOR_INT modes.
	(sparc_cannot_force_const_mem): Return false for CONST_VECTOR.
	(sparc_init_modes): Set sparc_mode_class to SF_MODE or DF_MODE for
	MODE_VECTOR_INT modes.
	(sparc_extra_constraint_check): Add new constraint 'Y'.
	* config/sparc/sparc.h: Define UNITS_PER_SIMD_WORD to 8 for TARGET_VIS.
	* config/sparc/sparc.md (V32): New mode macro for 32-bit modes.
	(V64): New mode macro for 64-bit modes.
	(movsf): Use V32 for mode instead of SF.
	(movsf_insn_vis): Use V32 for mode instead of SF.  Add 'Y' constraint
	alongside 'G' constraint.
	(movdf): Use V64 for mode instead of DF.
	(movdf_insn_v9only_vis, modf_insn_sp64_vis): Use V64 for mode instead
	of DF.  Add 'Y' constraint alongside 'G' constraint.
	(multi-isn and misaligned mems DFmode splitters): Use V64 for mode
	instead of DF.

Co-Authored-By: Eric Botcazou <ebotcazou@libertysurf.fr>

From-SVN: r90348
parent 26a89301
Showing with 70 additions and 6 deletions
gcc/ChangeLog
2004-11-09 James A. Morrison <phython@gcc.gnu.org>
Eric Botcazou <ebotcazou@libertysurf.fr>
PR target/18230
* doc/md.texi (SPARC constraints): Document 'Y' constraint.
* config/sparc/sparc-modes.def: Add vector modes of 4 and 8 bytes.
* config/sparc/sparc.c (sparc_vector_mode_supported_p): New function.
(TARGET_VECTOR_MODE_SUPPORTED_P): Set to sparc_vector_mode_supported_p.
(fp_zero_operand): Accept MODE_VECTOR_INT modes.
(input_operand): Accept CONST_VECTOR with MODE_VECTOR_INT modes.
(sparc_cannot_force_const_mem): Return false for CONST_VECTOR.
(sparc_init_modes): Set sparc_mode_class to SF_MODE or DF_MODE for
MODE_VECTOR_INT modes.
(sparc_extra_constraint_check): Add new constraint 'Y'.
* config/sparc/sparc.h: Define UNITS_PER_SIMD_WORD to 8 for TARGET_VIS.
* config/sparc/sparc.md (V32): New mode macro for 32-bit modes.
(V64): New mode macro for 64-bit modes.
(movsf): Use V32 for mode instead of SF.
(movsf_insn_vis): Use V32 for mode instead of SF. Add 'Y' constraint
alongside 'G' constraint.
(movdf): Use V64 for mode instead of DF.
(movdf_insn_v9only_vis, modf_insn_sp64_vis): Use V64 for mode instead
of DF. Add 'Y' constraint alongside 'G' constraint.
(multi-isn and misaligned mems DFmode splitters): Use V64 for mode
instead of DF.
2004-11-09 Ulrich Weigand <uweigand@de.ibm.com>
* config/s390/s390.c (s390_select_ccmode): Return CCAPmode for
......
gcc/config/sparc/sparc-modes.def
/* Definitions of target machine for GCC, for Sun SPARC.
Copyright (C) 2002 Free Software Foundation, Inc.
Copyright (C) 2002, 2004 Free Software Foundation, Inc.
Contributed by Michael Tiemann (tiemann@cygnus.com).
64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
at Cygnus Support.
......@@ -42,3 +42,7 @@ CC_MODE (CC_NOOV);
CC_MODE (CCX_NOOV);
CC_MODE (CCFP);
CC_MODE (CCFPE);
/* Vector modes. */
VECTOR_MODES (INT, 8); /* V8QI V4HI V2SI */
VECTOR_MODES (INT, 4); /* V4QI V2HI */
gcc/config/sparc/sparc.c
......@@ -348,6 +348,7 @@ static rtx sparc_struct_value_rtx (tree, int);
static bool sparc_return_in_memory (tree, tree);
static bool sparc_strict_argument_naming (CUMULATIVE_ARGS *);
static tree sparc_gimplify_va_arg (tree, tree, tree *, tree *);
static bool sparc_vector_mode_supported_p (enum machine_mode);
static bool sparc_pass_by_reference (CUMULATIVE_ARGS *,
enum machine_mode, tree, bool);
#ifdef SUBTARGET_ATTRIBUTE_TABLE
......@@ -466,6 +467,9 @@ enum processor_type sparc_cpu;
#undef TARGET_GIMPLIFY_VA_ARG_EXPR
#define TARGET_GIMPLIFY_VA_ARG_EXPR sparc_gimplify_va_arg
#undef TARGET_VECTOR_MODE_SUPPORTED_P
#define TARGET_VECTOR_MODE_SUPPORTED_P sparc_vector_mode_supported_p
#ifdef SUBTARGET_INSERT_ATTRIBUTES
#undef TARGET_INSERT_ATTRIBUTES
#define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
......@@ -769,7 +773,8 @@ const1_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
int
fp_zero_operand (rtx op, enum machine_mode mode)
{
if (GET_MODE_CLASS (GET_MODE (op)) != MODE_FLOAT)
enum mode_class mclass = GET_MODE_CLASS (GET_MODE (op));
if (mclass != MODE_FLOAT && mclass != MODE_VECTOR_INT)
return 0;
return op == CONST0_RTX (mode);
}
......@@ -1498,6 +1503,8 @@ clobbered_register (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
int
input_operand (rtx op, enum machine_mode mode)
{
enum mode_class mclass;
/* If both modes are non-void they must be the same. */
if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
return 0;
......@@ -1538,8 +1545,9 @@ input_operand (rtx op, enum machine_mode mode)
if (register_operand (op, mode))
return 1;
if (GET_MODE_CLASS (mode) == MODE_FLOAT
&& GET_CODE (op) == CONST_DOUBLE)
mclass = GET_MODE_CLASS (mode);
if ((mclass == MODE_FLOAT && GET_CODE (op) == CONST_DOUBLE)
|| (mclass == MODE_VECTOR_INT && GET_CODE (op) == CONST_VECTOR))
return 1;
/* If this is a SUBREG, look inside so that we handle
......@@ -3293,6 +3301,7 @@ sparc_cannot_force_const_mem (rtx x)
{
case CONST_INT:
case CONST_DOUBLE:
case CONST_VECTOR:
/* Accept all non-symbolic constants. */
return false;
......@@ -4181,6 +4190,12 @@ sparc_init_modes (void)
else
sparc_mode_class[i] = 0;
break;
case MODE_VECTOR_INT:
if (GET_MODE_SIZE (i) <= 4)
sparc_mode_class[i] = 1 << (int)SF_MODE;
else if (GET_MODE_SIZE (i) == 8)
sparc_mode_class[i] = 1 << (int)DF_MODE;
break;
case MODE_FLOAT:
case MODE_COMPLEX_FLOAT:
if (GET_MODE_SIZE (i) <= 4)
......@@ -6263,6 +6278,15 @@ sparc_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
return build_va_arg_indirect_ref (addr);
}
/* Implement the TARGET_VECTOR_MODE_SUPPORTED_P target hook.
Specify whether the vector mode is supported by the hardware. */
static bool
sparc_vector_mode_supported_p (enum machine_mode mode)
{
return TARGET_VIS && VECTOR_MODE_P (mode) ? true : false;
}
/* Return the string to output an unconditional branch to LABEL, which is
the operand number of the label.
......@@ -8445,6 +8469,9 @@ sparc_extra_constraint_check (rtx op, int c, int strict)
case 'T':
break;
case 'Y':
return fp_zero_operand (op, GET_MODE (op));
default:
return 0;
}
......
gcc/config/sparc/sparc.h
......@@ -769,6 +769,8 @@ extern struct sparc_cpu_select sparc_select[];
#define MIN_UNITS_PER_WORD 4
#endif
#define UNITS_PER_SIMD_WORD (TARGET_VIS ? 8 : 0)
/* Now define the sizes of the C data types. */
#define SHORT_TYPE_SIZE 16
......@@ -2042,7 +2044,9 @@ do { \
integer register, needed for ldd/std instructions.
'W' handles the memory operand when moving operands in/out
of 'e' constraint floating point registers. */
of 'e' constraint floating point registers.
'Y' handles the zero vector constant. */
#ifndef REG_OK_STRICT
......
gcc/doc/md.texi
......@@ -2367,7 +2367,10 @@ Memory address aligned to an 8-byte boundary
Even register
@item W
Memory address for @samp{e} constraint registers.
Memory address for @samp{e} constraint registers
@item Y
Vector zero
@end table
......
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