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riscv-gcc-1
Commit c6f709ec by Nick Clifton
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rl78-real.md (cbranchsi4_real_signed): Add anti-cacnonical alternatives. 

	* config/rl78/rl78-real.md (cbranchsi4_real_signed): Add
	anti-cacnonical alternatives.
	(negandhi3_real): New pattern.
	* config/rl78/rl78-virt.md (negandhi3_virt): New pattern.

From-SVN: r208282
parent 5752f78f
Showing with 127 additions and 33 deletions
gcc/ChangeLog
2014-03-03 Nick Clifton <nickc@redhat.com>
* config/rl78/rl78-real.md (cbranchsi4_real_signed): Add
anti-cacnonical alternatives.
(negandhi3_real): New pattern.
* config/rl78/rl78-virt.md (negandhi3_virt): New pattern.
2014-03-03 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
* config/avr/avr-mcus.def: Remove atxmega16x1.
......@@ -36,7 +43,7 @@
group, also set all symbols to local.
2014-03-02 Jan Hubicka <hubicka@ucw.cz>
PR ipa/60306
Revert:
......@@ -51,9 +58,9 @@
PR bootstrap/52466
PR target/46898
* config/lm32/lm32.c (lm32_legitimate_constant_p): Remove, as incorrect.
(TARGET_LEGITIMATE_CONSTANT_P): Undefine, as not needed.
(TARGET_LEGITIMATE_CONSTANT_P): Undefine, as not needed.
* config/lm32/lm32.md (movsi_insn): Add 32-bit immediate support.
(simple_return, *simple_return): New patterns
(simple_return, *simple_return): New patterns
* config/lm32/predicates.md (movsi_rhs_operand): Remove as obsolete.
* configure.ac (force_sjlj_exceptions): Force sjlj exceptions for lm32.
......
gcc/config/msp430/msp430-protos.h
......@@ -30,9 +30,11 @@ const char * msp430x_extendhisi (rtx *);
void msp430_fixup_compare_operands (enum machine_mode, rtx *);
int msp430_hard_regno_mode_ok (int, enum machine_mode);
int msp430_hard_regno_nregs (int, enum machine_mode);
bool msp430_hwmult_enabled (void);
rtx msp430_incoming_return_addr_rtx (void);
void msp430_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree, int);
int msp430_initial_elimination_offset (int, int);
bool msp430_is_f5_mcu (void);
bool msp430_is_interrupt_func (void);
const char * msp430x_logical_shift_right (rtx);
const char * msp430_mcu_name (void);
......@@ -41,7 +43,7 @@ void msp430_output_labelref (FILE *, const char *);
void msp430_register_pragmas (void);
rtx msp430_return_addr_rtx (int);
void msp430_split_movsi (rtx *);
rtx msp430_subreg (enum machine_mode, rtx, enum machine_mode, int);
void msp430_start_function (FILE *, const char *, tree);
rtx msp430_subreg (enum machine_mode, rtx, enum machine_mode, int);
#endif /* GCC_MSP430_PROTOS_H */
gcc/config/msp430/msp430.h
......@@ -407,3 +407,5 @@ typedef struct
#undef ASM_DECLARE_FUNCTION_NAME
#define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
msp430_start_function ((FILE), (NAME), (DECL))
#define TARGET_HAS_NO_HW_DIVIDE (! TARGET_HWMULT)
gcc/config/msp430/msp430.md
......@@ -48,7 +48,7 @@
UNS_REFSYM_NEED_EXIT
])
(include "predicates.md")
(include "constraints.md")
......@@ -144,19 +144,20 @@
(define_insn "grow_and_swap"
[(unspec_volatile [(const_int 0)] UNS_GROW_AND_SWAP)]
""
{ if (TARGET_LARGE)
return "SUBA\t#2, r1 \n MOVX.A\t2(r1), 0(r1)";
return "SUB\t#2, r1 \n MOV.W\t2(r1), 0(r1)";
}
)
"*
if (TARGET_LARGE)
return \"SUBA\t#2, r1 { MOVX.A\t2(r1), 0(r1)\";
return \"SUB\t#2, r1 { MOV.W\t2(r1), 0(r1)\";
"
)
(define_insn "swap_and_shrink"
[(unspec_volatile [(const_int 0)] UNS_SWAP_AND_SHRINK)]
""
{ return TARGET_LARGE
? "MOVX.A\t0(r1), 2(r1) \n ADDA\t#2, SP"
: "MOV.W\t0(r1), 2(r1) \n ADD\t#2, SP";
})
"* return TARGET_LARGE
? \"MOVX.A\t0(r1), 2(r1) { ADDA\t#2, SP\"
: \"MOV.W\t0(r1), 2(r1) { ADD\t#2, SP\";
")
; I set LOAD_EXTEND_OP and WORD_REGISTER_OPERATIONS, but gcc puts in a
; zero_extend anyway. Catch it here.
......@@ -1315,3 +1316,55 @@
return \"SUB.W\t#0, %0 { AND.W\t%2, %0\";
"
)
(define_insn "mulhisi3"
[(set (match_operand:SI 0 "register_operand" "=r")
(mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
(sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
"optimize > 2 && msp430_hwmult_enabled ()"
"*
if (msp430_is_f5_mcu ())
return \"MOV.W %1, &0x04C2 { MOV.W %2, &0x04C8 { MOV.W &0x04CA, %L0 { MOV.W &0x04CC, %H0\";
else
return \"MOV.W %1, &0x0132 { MOV.W %2, &0x0138 { MOV.W &0x013A, %L0 { MOV.W &0x013C, %H0\";
"
)
(define_insn "umulhisi3"
[(set (match_operand:SI 0 "register_operand" "=r")
(mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0"))
(zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
"optimize > 2 && msp430_hwmult_enabled ()"
"*
if (msp430_is_f5_mcu ())
return \"MOV.W %1, &0x04C0 { MOV.W %2, &0x04C8 { MOV.W &0x04CA, %L0 { MOV.W &0x04CC, %H0\";
else
return \"MOV.W %1, &0x0130 { MOV.W %2, &0x0138 { MOV.W &0x013A, %L0 { MOV.W &0x013C, %H0\";
"
)
(define_insn "mulsidi3"
[(set (match_operand:DI 0 "register_operand" "=r")
(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%0"))
(sign_extend:DI (match_operand:SI 2 "register_operand" "r"))))]
"optimize > 2 && msp430_hwmult_enabled ()"
"*
if (msp430_is_f5_mcu ())
return \"MOV.W %L1, &0x04D4 { MOV.W %H1, &0x04D6 { MOV.W %L2, &0x04E0 { MOV.W %H2, &0x04E2 { MOV.W &0x04E4, %A0 { MOV.W &0x04E6, %B0 { MOV.W &0x04E8, %C0 { MOV.W &0x04EA, %D0\";
else
return \"MOV.W %L1, &0x0144 { MOV.W %H1, &0x0146 { MOV.W %L2, &0x0150 { MOV.W %H2, &0x0152 { MOV.W &0x0154, %A0 { MOV.W &0x0156, %B0 { MOV.W &0x0158, %C0 { MOV.W &0x015A, %D0\";
"
)
(define_insn "umulsidi3"
[(set (match_operand:DI 0 "register_operand" "=r")
(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
(zero_extend:DI (match_operand:SI 2 "register_operand" "r"))))]
"optimize > 2 && msp430_hwmult_enabled ()"
"*
if (msp430_is_f5_mcu ())
return \"MOV.W %L1, &0x04D0 { MOV.W %H1, &0x04D2 { MOV.W %L2, &0x04E0 { MOV.W %H2, &0x04E2 { MOV.W &0x04E4, %A0 { MOV.W &0x04E6, %B0 { MOV.W &0x04E8, %C0 { MOV.W &0x04EA, %D0\";
else
return \"MOV.W %L1, &0x0140 { MOV.W %H1, &0x0141 { MOV.W %L2, &0x0150 { MOV.W %H2, &0x0152 { MOV.W &0x0154, %A0 { MOV.W &0x0156, %B0 { MOV.W &0x0158, %C0 { MOV.W &0x015A, %D0\";
"
)
gcc/config/msp430/msp430.opt
......@@ -7,7 +7,7 @@ Target Mask(ASM_HEX)
Force assembly output to always use hex constants
mmcu=
Target Joined RejectNegative Var(target_mcu)
Target ToLower Joined RejectNegative Var(target_mcu)
Specify the MCU to build for.
mcpu=
......@@ -32,3 +32,7 @@ Target Undocumented Mask(OPT_SPACE)
minrt
Target Report Mask(MINRT) RejectNegative
Use a minimum runtime (no static initializers or ctors) for memory-constrained devices.
mhwmult
Target Report Var(ENABLE_HWMULT, 1) Init(1)
Enable hardware multiply (except in interrupt routines)
gcc/config/rl78/rl78-expand.md
......@@ -237,9 +237,9 @@
)
(define_expand "ashlsi3"
[(parallel [(set (match_operand:SI 0 "nonimmediate_operand")
(ashift:SI (match_operand:SI 1 "nonimmediate_operand")
(match_operand:SI 2 "nonmemory_operand")))
[(parallel [(set (match_operand:SI 0 "nonimmediate_operand")
(ashift:SI (match_operand:SI 1 "nonimmediate_operand")
(match_operand:SI 2 "nonmemory_operand")))
(clobber (reg:HI X_REG))])
]
""
......
gcc/config/rl78/rl78-real.md
......@@ -127,9 +127,9 @@
)
(define_insn "*addqihi3a_real"
[(set (match_operand:HI 0 "register_operand" "=r")
(plus:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%r"))
(match_operand:HI 2 "register_operand" "r")))
[(set (match_operand:HI 0 "register_operand" "=r")
(plus:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
(match_operand:HI 2 "register_operand" "0")))
]
"rl78_real_insns_ok ()"
"add\t%q0, %q1 \;addc\t%Q0, #0"
......@@ -411,8 +411,8 @@
(define_insn "*cbranchsi4_real_signed"
[(set (pc) (if_then_else
(match_operator 0 "rl78_cmp_operator_signed"
[(match_operand:SI 1 "nonimmediate_operand" "vU,vU,vU")
(match_operand:SI 2 "nonmemory_operand" "ISsi,i,v")])
[(match_operand:SI 1 "general_operand" "vU,vU,vU,i,i")
(match_operand:SI 2 "nonmemory_operand" "ISsi,i,v,S,v")])
(label_ref (match_operand 3 "" ""))
(pc)))
(clobber (reg:HI AX_REG))
......@@ -421,7 +421,9 @@
"@
movw ax,%H1 \;cmpw ax, %H2 \;xor1 CY,a.7\;not1 CY\; movw ax,%h1 \;sknz \;cmpw ax, %h2 \;sk%C0 \;br\t!!%3
movw ax,%H1 \;cmpw ax, %H2 \;xor1 CY,a.7\; movw ax,%h1 \;sknz \;cmpw ax, %h2 \;sk%C0 \;br\t!!%3
movw ax,%H1 \;cmpw ax, %H2 \;xor1 CY,a.7\;xor1 CY,%E2.7\;movw ax,%h1 \;sknz \;cmpw ax, %h2 \;sk%C0 \;br\t!!%3"
movw ax,%H1 \;cmpw ax, %H2 \;xor1 CY,a.7\;xor1 CY,%E2.7\;movw ax,%h1 \;sknz \;cmpw ax, %h2 \;sk%C0 \;br\t!!%3
movw ax, %H1\; cmpw ax, %H2\; xor1 CY, a.7\; not1 CY\; movw ax, %h1 \;sknz\; cmpw ax, %h2 \;sk%0 \;br\t!!%3
movw ax, %H1\; cmpw ax, %H2\; xor1 CY, a.7\; movw ax, %h1\; sknz\; cmpw ax, %h2\; sk%0\; br\t!!%3"
)
(define_insn "*cbranchsi4_real"
......@@ -549,3 +551,11 @@
[(set (reg:QI A_REG) (and:QI (reg:QI A_REG) (match_dup 1)))]
)
(define_insn "*negandhi3_real"
[(set (match_operand:HI 0 "register_operand" "=A")
(and:HI (neg:HI (match_operand:HI 1 "register_operand" "0"))
(match_operand:HI 2 "immediate_operand" "n")))
]
"rl78_real_insns_ok ()"
"xor a, #0xff @ xch a, x @ xor a, #0xff @ xch a, x @ addw ax, #1 @ and a, %Q2 @ xch a, x @ and a, %q2 @ xch a, x"
)
gcc/config/rl78/rl78-virt.md
......@@ -405,3 +405,12 @@
]
"rl78_setup_peep_movhi (operands);"
)
(define_insn "*negandhi3_virt"
[(set (match_operand:HI 0 "register_operand" "=v")
(and:HI (neg:HI (match_operand:HI 1 "register_operand" "0"))
(match_operand:HI 2 "immediate_operand" "n")))
]
"rl78_virt_insns_ok ()"
"v.nand\t%0, %1, %2"
)
gcc/config/rx/rx.md
......@@ -2625,7 +2625,7 @@
(define_insn "movdi"
[(set:DI (match_operand:DI 0 "nonimmediate_operand" "=rm")
(match_operand:DI 1 "general_operand" "rmi"))]
"TARGET_ENABLE_LRA || 1"
"TARGET_ENABLE_LRA"
{ return rx_gen_move_template (operands, false); }
[(set_attr "length" "16")
(set_attr "timings" "22")]
......@@ -2634,7 +2634,7 @@
(define_insn "movdf"
[(set:DF (match_operand:DF 0 "nonimmediate_operand" "=rm")
(match_operand:DF 1 "general_operand" "rmi"))]
"TARGET_ENABLE_LRA || 1"
"TARGET_ENABLE_LRA"
{ return rx_gen_move_template (operands, false); }
[(set_attr "length" "16")
(set_attr "timings" "22")]
......
gcc/doc/invoke.texi
......@@ -18167,18 +18167,25 @@ post- fixed with @code{__}. This in turn will be used by the
@code{msp430.h} header file to select an MCU specific supplimentary
header file.
In addition two scripts will be added to the linker command line:
@code{memory.ld} and @code{peripherals.ld}, with a search path based
upon the MCU name.
The option also sets the ISA to use. If the MCU name is one that is
known to only support the 430 ISA then that is selected, otherwise the
430X ISA is selected. A generic MCU name of @code{msp430} can also be
used to select the 430 ISA. Similarly the generic @code{msp430x} MCU
name will select the 430X ISA.
In addition an MCU specific linker script will be added to the linker
command line. The script's name is the name of the MCU with
@code{.ld} appended. Thus specifying @option{-mmcu=xxx} on the gcc
command line will define the C preprocessor symbol @code{__XXX__} and
cause the linker to search for a script called @file{xxx.ld}.
This option is also passed on to the assembler.
@item -mcpu=
@opindex -mcpu=
Specific the ISA to use. Accepted values are @code{msp430},
@code{msp430x} and @code{msp430xv2}. This option is needed in order
to ensure that the correct instructions are generated and that the
correct libraries are linked in.
Specifies the ISA to use. Accepted values are @code{msp430},
@code{msp430x} and @code{msp430xv2}. This option is deprecated. The
@option{-mmcu=} option should be used to select the ISA.
@item -msim
@opindex msim
......
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