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Commit c6eb38f3 by Michael Meissner Committed by Michael Meissner
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re PR target/78597 (test case gcc.dg/torture/fp-int-convert-float128-ieee.c (and… 

re PR target/78597 (test case gcc.dg/torture/fp-int-convert-float128-ieee.c (and others) fail starting with r242780)

2017-01-31  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/78597
	PR target/79038
	* config/rs6000/rs6000-protos.h (convert_float128_to_int): Delete,
	no longer used.
	(convert_int_to_float128): Likewise.
	* config/rs6000/rs6000.c (convert_float128_to_int): Likewise.
	(convert_int_to_float128): Likewise.
	* config/rs6000/rs6000.md (UNSPEC_IEEE128_MOVE): Likewise.
	(UNSPEC_IEEE128_CONVERT): Likewise.
	(floatsi<mode>2, FLOAT128 iterator): Bypass calling
	rs6000_expand_float128_convert if we have IEEE 128-bit hardware.
	Use local variables for IBM extended format.
	(fix_trunc<mode>si2, FLOAT128 iterator): Likewise.
	(fix_trunc<mode>si2_fprs): Likewise.
	(fixuns_trunc<IEEE128:mode><SDI:mode>2): Likewise.
	(floatuns<IEEE128:mode>2, IEEE128 iterator): Likewise.
	(fix<uns>_<mode>si2_hw): Rework the IEEE 128-bt hardware support
	to know that we can now have integers of all sizes in vector
	registers.
	(fix<uns>_<mode>di2_hw): Likewise.
	(float<uns>_<mode>si2_hw): Likewise.
	(fix_<mode>si2_hw): Likewise.
	(fixuns_<mode>si2_hw): Likewise.
	(float<uns>_<mode>di2_hw): Likewise.
	(float_<mode>di2_hw): Likewise.
	(float_<mode>si2_hw): Likewise.
	(floatuns_<mode>di2_hw): Likewise.
	(floatuns_<mode>si2_hw): Likewise.
	(xscvqp<su>wz_<mode>): Delete, no longer used.
	(xscvqp<su>dz_<mode>): Likewise.
	(xscv<su>dqp_<mode>): Likewise.
	(ieee128_mfvsrd_64bit): Likewise.
	(ieee128_mfvsrd_32bit): Likewise.
	(ieee128_mfvsrwz): Likewise.
	(ieee128_mtvsrw): Likewise.
	(ieee128_mtvsrd_64bit): Likewise.
	(ieee128_mtvsrd_32bit): Likewise.

From-SVN: r245059
parent a0a348b1
Showing with 40 additions and 88 deletions
gcc/ChangeLog
2017-01-31 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/78597
PR target/79038
* config/rs6000/rs6000-protos.h (convert_float128_to_int): Delete,
no longer used.
(convert_int_to_float128): Likewise.
* config/rs6000/rs6000.c (convert_float128_to_int): Likewise.
(convert_int_to_float128): Likewise.
* config/rs6000/rs6000.md (UNSPEC_IEEE128_MOVE): Likewise.
(UNSPEC_IEEE128_CONVERT): Likewise.
(floatsi<mode>2, FLOAT128 iterator): Bypass calling
rs6000_expand_float128_convert if we have IEEE 128-bit hardware.
Use local variables for IBM extended format.
(fix_trunc<mode>si2, FLOAT128 iterator): Likewise.
(fix_trunc<mode>si2_fprs): Likewise.
(fixuns_trunc<IEEE128:mode><SDI:mode>2): Likewise.
(floatuns<IEEE128:mode>2, IEEE128 iterator): Likewise.
(fix<uns>_<mode>si2_hw): Rework the IEEE 128-bt hardware support
to know that we can now have integers of all sizes in vector
registers.
(fix<uns>_<mode>di2_hw): Likewise.
(float<uns>_<mode>si2_hw): Likewise.
(fix_<mode>si2_hw): Likewise.
(fixuns_<mode>si2_hw): Likewise.
(float<uns>_<mode>di2_hw): Likewise.
(float_<mode>di2_hw): Likewise.
(float_<mode>si2_hw): Likewise.
(floatuns_<mode>di2_hw): Likewise.
(floatuns_<mode>si2_hw): Likewise.
(xscvqp<su>wz_<mode>): Delete, no longer used.
(xscvqp<su>dz_<mode>): Likewise.
(xscv<su>dqp_<mode>): Likewise.
(ieee128_mfvsrd_64bit): Likewise.
(ieee128_mfvsrd_32bit): Likewise.
(ieee128_mfvsrwz): Likewise.
(ieee128_mtvsrw): Likewise.
(ieee128_mtvsrd_64bit): Likewise.
(ieee128_mtvsrd_32bit): Likewise.
2017-01-31 Martin Liska <mliska@suse.cz>
PR ipa/79285
......
gcc/config/rs6000/rs6000-protos.h
......@@ -57,8 +57,6 @@ extern const char *rs6000_output_move_128bit (rtx *);
extern bool rs6000_move_128bit_ok_p (rtx []);
extern bool rs6000_split_128bit_ok_p (rtx []);
extern void rs6000_expand_float128_convert (rtx, rtx, bool);
extern void convert_float128_to_int (rtx *, enum rtx_code);
extern void convert_int_to_float128 (rtx *, enum rtx_code);
extern void rs6000_expand_vector_init (rtx, rtx);
extern void paired_expand_vector_init (rtx, rtx);
extern void rs6000_expand_vector_set (rtx, rtx, int);
......
gcc/config/rs6000/rs6000.c
......@@ -24686,92 +24686,6 @@ rs6000_expand_float128_convert (rtx dest, rtx src, bool unsigned_p)
return;
}
/* Split a conversion from __float128 to an integer type into separate insns.
OPERANDS points to the destination, source, and V2DI temporary
register. CODE is either FIX or UNSIGNED_FIX. */
void
convert_float128_to_int (rtx *operands, enum rtx_code code)
{
rtx dest = operands[0];
rtx src = operands[1];
rtx tmp = operands[2];
rtx cvt;
rtvec cvt_vec;
rtx cvt_unspec;
rtvec move_vec;
rtx move_unspec;
if (GET_CODE (tmp) == SCRATCH)
tmp = gen_reg_rtx (V2DImode);
if (MEM_P (dest))
dest = rs6000_address_for_fpconvert (dest);
/* Generate the actual convert insn of the form:
(set (tmp) (unspec:V2DI [(fix:SI (reg:KF))] UNSPEC_IEEE128_CONVERT)). */
cvt = gen_rtx_fmt_e (code, GET_MODE (dest), src);
cvt_vec = gen_rtvec (1, cvt);
cvt_unspec = gen_rtx_UNSPEC (V2DImode, cvt_vec, UNSPEC_IEEE128_CONVERT);
emit_insn (gen_rtx_SET (tmp, cvt_unspec));
/* Generate the move insn of the form:
(set (dest:SI) (unspec:SI [(tmp:V2DI))] UNSPEC_IEEE128_MOVE)). */
move_vec = gen_rtvec (1, tmp);
move_unspec = gen_rtx_UNSPEC (GET_MODE (dest), move_vec, UNSPEC_IEEE128_MOVE);
emit_insn (gen_rtx_SET (dest, move_unspec));
}
/* Split a conversion from an integer type to __float128 into separate insns.
OPERANDS points to the destination, source, and V2DI temporary
register. CODE is either FLOAT or UNSIGNED_FLOAT. */
void
convert_int_to_float128 (rtx *operands, enum rtx_code code)
{
rtx dest = operands[0];
rtx src = operands[1];
rtx tmp = operands[2];
rtx cvt;
rtvec cvt_vec;
rtx cvt_unspec;
rtvec move_vec;
rtx move_unspec;
rtx unsigned_flag;
if (GET_CODE (tmp) == SCRATCH)
tmp = gen_reg_rtx (V2DImode);
if (MEM_P (src))
src = rs6000_address_for_fpconvert (src);
/* Generate the move of the integer into the Altivec register of the form:
(set (tmp:V2DI) (unspec:V2DI [(src:SI)
(const_int 0)] UNSPEC_IEEE128_MOVE)).
or:
(set (tmp:V2DI) (unspec:V2DI [(src:DI)] UNSPEC_IEEE128_MOVE)). */
if (GET_MODE (src) == SImode)
{
unsigned_flag = (code == UNSIGNED_FLOAT) ? const1_rtx : const0_rtx;
move_vec = gen_rtvec (2, src, unsigned_flag);
}
else
move_vec = gen_rtvec (1, src);
move_unspec = gen_rtx_UNSPEC (V2DImode, move_vec, UNSPEC_IEEE128_MOVE);
emit_insn (gen_rtx_SET (tmp, move_unspec));
/* Generate the actual convert insn of the form:
(set (dest:KF) (float:KF (unspec:DI [(tmp:V2DI)]
UNSPEC_IEEE128_CONVERT))). */
cvt_vec = gen_rtvec (1, tmp);
cvt_unspec = gen_rtx_UNSPEC (DImode, cvt_vec, UNSPEC_IEEE128_CONVERT);
cvt = gen_rtx_fmt_e (code, GET_MODE (dest), cvt_unspec);
emit_insn (gen_rtx_SET (dest, cvt));
}
/* Emit the RTL for an sISEL pattern. */
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