Skip to content

R
riscv-gcc-1
Commit c6dd76fa by Segher Boessenkool Committed by Segher Boessenkool
Options

rs6000: wk -> ws+p8v 


	* config/rs6000/constraints.md (define_register_constraint "wk"):
	Delete.
	* config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete
	RS6000_CONSTRAINT_wk.
	* config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust.
	(rs6000_init_hard_regno_mode_ok): Adjust.
	* config/rs6000/rs6000.md: Replace "wk" constraint by "ws" with "p8v".
	* doc/md.texi (Machine Constraints): Adjust.

From-SVN: r271485
parent 818502a3
Showing with 14 additions and 17 deletions
gcc/ChangeLog
2019-05-21 Segher Boessenkool <segher@kernel.crashing.org> 2019-05-21 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/constraints.md (define_register_constraint "wk"):
Delete.
* config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete
RS6000_CONSTRAINT_wk.
* config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust.
(rs6000_init_hard_regno_mode_ok): Adjust.
* config/rs6000/rs6000.md: Replace "wk" constraint by "ws" with "p8v".
* doc/md.texi (Machine Constraints): Adjust.
2019-05-21 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/constraints.md (define_register_constraint "wj"): * config/rs6000/constraints.md (define_register_constraint "wj"):
Delete. Delete.
* config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete
......
gcc/config/rs6000/constraints.md
...@@ -74,9 +74,6 @@ ...@@ -74,9 +74,6 @@
(define_register_constraint "wi" "rs6000_constraints[RS6000_CONSTRAINT_wi]" (define_register_constraint "wi" "rs6000_constraints[RS6000_CONSTRAINT_wi]"
"FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.") "FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.")
(define_register_constraint "wk" "rs6000_constraints[RS6000_CONSTRAINT_wk]"
"FP or VSX register to hold 64-bit doubles for direct moves or NO_REGS.")
(define_register_constraint "wl" "rs6000_constraints[RS6000_CONSTRAINT_wl]" (define_register_constraint "wl" "rs6000_constraints[RS6000_CONSTRAINT_wl]"
"Floating point register if the LFIWAX instruction is enabled or NO_REGS.") "Floating point register if the LFIWAX instruction is enabled or NO_REGS.")
......
gcc/config/rs6000/rs6000.c
...@@ -2513,7 +2513,6 @@ rs6000_debug_reg_global (void) ...@@ -2513,7 +2513,6 @@ rs6000_debug_reg_global (void)
"wf reg_class = %s\n" "wf reg_class = %s\n"
"wg reg_class = %s\n" "wg reg_class = %s\n"
"wi reg_class = %s\n" "wi reg_class = %s\n"
"wk reg_class = %s\n"
"wl reg_class = %s\n" "wl reg_class = %s\n"
"wm reg_class = %s\n" "wm reg_class = %s\n"
"wp reg_class = %s\n" "wp reg_class = %s\n"
...@@ -2536,7 +2535,6 @@ rs6000_debug_reg_global (void) ...@@ -2536,7 +2535,6 @@ rs6000_debug_reg_global (void)
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wg]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wg]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wi]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wi]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wk]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wl]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wl]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wm]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wm]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wp]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wp]],
...@@ -3160,7 +3158,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) ...@@ -3160,7 +3158,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
wf - Preferred register class for V4SFmode. wf - Preferred register class for V4SFmode.
wg - Float register for power6x move insns. wg - Float register for power6x move insns.
wi - FP or VSX register to hold 64-bit integers for VSX insns. wi - FP or VSX register to hold 64-bit integers for VSX insns.
wk - FP or VSX register to hold 64-bit doubles for direct moves.
wl - Float register if we can do 32-bit signed int loads. wl - Float register if we can do 32-bit signed int loads.
wm - VSX register for ISA 2.07 direct move operations. wm - VSX register for ISA 2.07 direct move operations.
wn - always NO_REGS. wn - always NO_REGS.
...@@ -3201,11 +3198,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) ...@@ -3201,11 +3198,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
rs6000_constraints[RS6000_CONSTRAINT_wl] = FLOAT_REGS; /* DImode */ rs6000_constraints[RS6000_CONSTRAINT_wl] = FLOAT_REGS; /* DImode */
if (TARGET_DIRECT_MOVE) if (TARGET_DIRECT_MOVE)
{ rs6000_constraints[RS6000_CONSTRAINT_wm] = VSX_REGS;
rs6000_constraints[RS6000_CONSTRAINT_wk] /* DFmode */
= rs6000_constraints[RS6000_CONSTRAINT_ws];
rs6000_constraints[RS6000_CONSTRAINT_wm] = VSX_REGS;
}
if (TARGET_POWERPC64) if (TARGET_POWERPC64)
{ {
gcc/config/rs6000/rs6000.h
...@@ -1254,7 +1254,6 @@ enum r6000_reg_class_enum { ...@@ -1254,7 +1254,6 @@ enum r6000_reg_class_enum {
RS6000_CONSTRAINT_wf, /* VSX register for V4SF */ RS6000_CONSTRAINT_wf, /* VSX register for V4SF */
RS6000_CONSTRAINT_wg, /* FPR register for -mmfpgpr */ RS6000_CONSTRAINT_wg, /* FPR register for -mmfpgpr */
RS6000_CONSTRAINT_wi, /* FPR/VSX register to hold DImode */ RS6000_CONSTRAINT_wi, /* FPR/VSX register to hold DImode */
RS6000_CONSTRAINT_wk, /* FPR/VSX register for DFmode direct moves. */
RS6000_CONSTRAINT_wl, /* FPR register for LFIWAX */ RS6000_CONSTRAINT_wl, /* FPR register for LFIWAX */
RS6000_CONSTRAINT_wm, /* VSX register for direct move */ RS6000_CONSTRAINT_wm, /* VSX register for direct move */
RS6000_CONSTRAINT_wp, /* VSX reg for IEEE 128-bit fp TFmode. */ RS6000_CONSTRAINT_wp, /* VSX reg for IEEE 128-bit fp TFmode. */
......
gcc/config/rs6000/rs6000.md
...@@ -471,7 +471,7 @@ ...@@ -471,7 +471,7 @@
(define_mode_attr f64_vsx [(DF "ws") (DD "wn")]) (define_mode_attr f64_vsx [(DF "ws") (DD "wn")])
; Definitions for 64-bit direct move ; Definitions for 64-bit direct move
(define_mode_attr f64_dm [(DF "wk") (DD "d")]) (define_mode_attr f64_dm [(DF "ws") (DD "d")])
; Definitions for 64-bit use of altivec registers ; Definitions for 64-bit use of altivec registers
(define_mode_attr f64_av [(DF "wv") (DD "wn")]) (define_mode_attr f64_av [(DF "wv") (DD "wn")])
......
gcc/doc/md.texi
...@@ -3197,7 +3197,7 @@ Altivec vector register ...@@ -3197,7 +3197,7 @@ Altivec vector register
Any VSX register if the @option{-mvsx} option was used or NO_REGS. Any VSX register if the @option{-mvsx} option was used or NO_REGS.
When using any of the register constraints (@code{wa}, @code{wd}, When using any of the register constraints (@code{wa}, @code{wd},
@code{wf}, @code{wg}, @code{wi}, @code{wk}, @code{wf}, @code{wg}, @code{wi},
@code{wl}, @code{wm}, @code{wp}, @code{wq}, @code{ws}, @code{wl}, @code{wm}, @code{wp}, @code{wq}, @code{ws},
@code{wt}, @code{wv}, or @code{ww}) @code{wt}, @code{wv}, or @code{ww})
that take VSX registers, you must use @code{%x<n>} in the template so that take VSX registers, you must use @code{%x<n>} in the template so
...@@ -3262,9 +3262,6 @@ If @option{-mmfpgpr} was used, a floating point register or NO_REGS. ...@@ -3262,9 +3262,6 @@ If @option{-mmfpgpr} was used, a floating point register or NO_REGS.
@item wi @item wi
FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS. FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.
@item wk
FP or VSX register to hold 64-bit doubles for direct moves or NO_REGS.
@item wl @item wl
Floating point register if the LFIWAX instruction is enabled or NO_REGS. Floating point register if the LFIWAX instruction is enabled or NO_REGS.
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment