Skip to content

R
riscv-gcc-1
Commit c5e16983 by Richard Sandiford Committed by Richard Sandiford
Options

[AArch64] Add SVE conditional conversion patterns 

This patch adds patterns to match conditional conversions between
integers and like-sized floats.  The patterns are actually more
general than that, but the other combinations can only be tested
via the ACLE.

2019-08-14  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/aarch64-sve.md
	(*cond_<SVE_COND_FCVTI:optab>_nontrunc<SVE_F:mode><SVE_HSDI:mode>)
	(*cond_<SVE_COND_ICVTF:optab>_nonextend<SVE_HSDI:mode><SVE_F:mode>):
	New patterns.

gcc/testsuite/
	* gcc.target/aarch64/sve/cond_convert_1.c: New test.
	* gcc.target/aarch64/sve/cond_convert_1_run.c: Likewise.
	* gcc.target/aarch64/sve/cond_convert_2.c: Likewise.
	* gcc.target/aarch64/sve/cond_convert_2_run.c: Likewise.
	* gcc.target/aarch64/sve/cond_convert_3.c: Likewise.
	* gcc.target/aarch64/sve/cond_convert_3_run.c: Likewise.
	* gcc.target/aarch64/sve/cond_convert_4.c: Likewise.
	* gcc.target/aarch64/sve/cond_convert_4_run.c: Likewise.
	* gcc.target/aarch64/sve/cond_convert_5.c: Likewise.
	* gcc.target/aarch64/sve/cond_convert_5_run.c: Likewise.
	* gcc.target/aarch64/sve/cond_convert_6.c: Likewise.
	* gcc.target/aarch64/sve/cond_convert_6_run.c: Likewise.

From-SVN: r274478
parent b21f7d53
Showing with 484 additions and 0 deletions
gcc/ChangeLog
2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
* config/aarch64/aarch64-sve.md
(*cond_<SVE_COND_FCVTI:optab>_nontrunc<SVE_F:mode><SVE_HSDI:mode>)
(*cond_<SVE_COND_ICVTF:optab>_nonextend<SVE_HSDI:mode><SVE_F:mode>):
New patterns.
2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
Kugan Vivekanandarajah <kugan.vivekanandarajah@linaro.org>
* config/aarch64/aarch64-sve.md
......
gcc/config/aarch64/aarch64-sve.md
......@@ -4071,6 +4071,39 @@
"fcvtz<su>\t%0.<VNx4SI_ONLY:Vetype>, %1/m, %2.<VNx2DF_ONLY:Vetype>"
)
;; Predicated float-to-integer conversion with merging, either to the same
;; width or wider.
;;
;; The first alternative doesn't need the earlyclobber, but the only case
;; it would help is the uninteresting one in which operands 2 and 3 are
;; the same register (despite having different modes). Making all the
;; alternatives earlyclobber makes things more consistent for the
;; register allocator.
(define_insn_and_rewrite "*cond_<optab>_nontrunc<SVE_F:mode><SVE_HSDI:mode>"
[(set (match_operand:SVE_HSDI 0 "register_operand" "=&w, &w, ?&w")
(unspec:SVE_HSDI
[(match_operand:<SVE_HSDI:VPRED> 1 "register_operand" "Upl, Upl, Upl")
(unspec:SVE_HSDI
[(match_operand 4)
(match_operand:SI 5 "aarch64_sve_gp_strictness")
(match_operand:SVE_F 2 "register_operand" "w, w, w")]
SVE_COND_FCVTI)
(match_operand:SVE_HSDI 3 "aarch64_simd_reg_or_zero" "0, Dz, w")]
UNSPEC_SEL))]
"TARGET_SVE
&& <SVE_HSDI:elem_bits> >= <SVE_F:elem_bits>
&& aarch64_sve_pred_dominates_p (&operands[4], operands[1])"
"@
fcvtz<su>\t%0.<SVE_HSDI:Vetype>, %1/m, %2.<SVE_F:Vetype>
movprfx\t%0.<SVE_HSDI:Vetype>, %1/z, %2.<SVE_HSDI:Vetype>\;fcvtz<su>\t%0.<SVE_HSDI:Vetype>, %1/m, %2.<SVE_F:Vetype>
movprfx\t%0, %3\;fcvtz<su>\t%0.<SVE_HSDI:Vetype>, %1/m, %2.<SVE_F:Vetype>"
"&& !rtx_equal_p (operands[1], operands[4])"
{
operands[4] = copy_rtx (operands[1]);
}
[(set_attr "movprfx" "*,yes,yes")]
)
;; -------------------------------------------------------------------------
;; ---- [INT<-FP] Packs
;; -------------------------------------------------------------------------
......@@ -4155,6 +4188,39 @@
"<su>cvtf\t%0.<VNx2DF_ONLY:Vetype>, %1/m, %2.<VNx4SI_ONLY:Vetype>"
)
;; Predicated integer-to-float conversion with merging, either to the same
;; width or narrower.
;;
;; The first alternative doesn't need the earlyclobber, but the only case
;; it would help is the uninteresting one in which operands 2 and 3 are
;; the same register (despite having different modes). Making all the
;; alternatives earlyclobber makes things more consistent for the
;; register allocator.
(define_insn_and_rewrite "*cond_<optab>_nonextend<SVE_HSDI:mode><SVE_F:mode>"
[(set (match_operand:SVE_F 0 "register_operand" "=&w, &w, ?&w")
(unspec:SVE_F
[(match_operand:<SVE_HSDI:VPRED> 1 "register_operand" "Upl, Upl, Upl")
(unspec:SVE_F
[(match_operand 4)
(match_operand:SI 5 "aarch64_sve_gp_strictness")
(match_operand:SVE_HSDI 2 "register_operand" "w, w, w")]
SVE_COND_ICVTF)
(match_operand:SVE_F 3 "aarch64_simd_reg_or_zero" "0, Dz, w")]
UNSPEC_SEL))]
"TARGET_SVE
&& <SVE_HSDI:elem_bits> >= <SVE_F:elem_bits>
&& aarch64_sve_pred_dominates_p (&operands[4], operands[1])"
"@
<su>cvtf\t%0.<SVE_F:Vetype>, %1/m, %2.<SVE_HSDI:Vetype>
movprfx\t%0.<SVE_HSDI:Vetype>, %1/z, %2.<SVE_HSDI:Vetype>\;<su>cvtf\t%0.<SVE_F:Vetype>, %1/m, %2.<SVE_HSDI:Vetype>
movprfx\t%0, %3\;<su>cvtf\t%0.<SVE_F:Vetype>, %1/m, %2.<SVE_HSDI:Vetype>"
"&& !rtx_equal_p (operands[1], operands[4])"
{
operands[4] = copy_rtx (operands[1]);
}
[(set_attr "movprfx" "*,yes,yes")]
)
;; -------------------------------------------------------------------------
;; ---- [FP<-INT] Packs
;; -------------------------------------------------------------------------
......
gcc/testsuite/ChangeLog
2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
* gcc.target/aarch64/sve/cond_convert_1.c: New test.
* gcc.target/aarch64/sve/cond_convert_1_run.c: Likewise.
* gcc.target/aarch64/sve/cond_convert_2.c: Likewise.
* gcc.target/aarch64/sve/cond_convert_2_run.c: Likewise.
* gcc.target/aarch64/sve/cond_convert_3.c: Likewise.
* gcc.target/aarch64/sve/cond_convert_3_run.c: Likewise.
* gcc.target/aarch64/sve/cond_convert_4.c: Likewise.
* gcc.target/aarch64/sve/cond_convert_4_run.c: Likewise.
* gcc.target/aarch64/sve/cond_convert_5.c: Likewise.
* gcc.target/aarch64/sve/cond_convert_5_run.c: Likewise.
* gcc.target/aarch64/sve/cond_convert_6.c: Likewise.
* gcc.target/aarch64/sve/cond_convert_6_run.c: Likewise.
2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
Kugan Vivekanandarajah <kugan.vivekanandarajah@linaro.org>
* gcc.target/aarch64/sve/cond_unary_1.c: Add tests for
......
gcc/testsuite/gcc.target/aarch64/sve/cond_convert_1.c 0 → 100644
/* { dg-do compile } */
/* { dg-options "-O2 -ftree-vectorize -fno-trapping-math" } */
#include <stdint.h>
#define DEF_LOOP(FLOAT_TYPE, INT_TYPE) \
void __attribute__ ((noipa)) \
test_##INT_TYPE (FLOAT_TYPE *__restrict r, \
INT_TYPE *__restrict a, \
FLOAT_TYPE *__restrict b, \
INT_TYPE *__restrict pred, int n) \
{ \
for (int i = 0; i < n; ++i) \
r[i] = pred[i] ? (FLOAT_TYPE) a[i] : b[i]; \
}
#define TEST_ALL(T) \
T (_Float16, int16_t) \
T (_Float16, uint16_t) \
T (float, int32_t) \
T (float, uint32_t) \
T (double, int64_t) \
T (double, uint64_t)
TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {\tscvtf\tz[0-9]+\.h, p[0-7]/m,} 1 } } */
/* { dg-final { scan-assembler-times {\tucvtf\tz[0-9]+\.h, p[0-7]/m,} 1 } } */
/* { dg-final { scan-assembler-times {\tscvtf\tz[0-9]+\.s, p[0-7]/m,} 1 } } */
/* { dg-final { scan-assembler-times {\tucvtf\tz[0-9]+\.s, p[0-7]/m,} 1 } } */
/* { dg-final { scan-assembler-times {\tscvtf\tz[0-9]+\.d, p[0-7]/m,} 1 } } */
/* { dg-final { scan-assembler-times {\tucvtf\tz[0-9]+\.d, p[0-7]/m,} 1 } } */
/* { dg-final { scan-assembler-not {\tmov\tz} } } */
/* At the moment we don't manage to avoid using MOVPRFX. */
/* { dg-final { scan-assembler-not {\tmovprfx\t} { xfail *-*-* } } } */
/* { dg-final { scan-assembler-not {\tsel\t} } } */
gcc/testsuite/gcc.target/aarch64/sve/cond_convert_1_run.c 0 → 100644
/* { dg-do run { target { aarch64_sve_hw } } } */
/* { dg-options "-O2 -ftree-vectorize -ftrapping-math" } */
#include "cond_convert_1.c"
#define N 99
#define TEST_LOOP(FLOAT_TYPE, INT_TYPE) \
{ \
FLOAT_TYPE r[N], b[N]; \
INT_TYPE a[N], pred[N]; \
for (int i = 0; i < N; ++i) \
{ \
a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : -1); \
b[i] = (i % 9) * (i % 7 + 1); \
pred[i] = (i % 7 < 4); \
asm volatile ("" ::: "memory"); \
} \
test_##INT_TYPE (r, a, b, pred, N); \
for (int i = 0; i < N; ++i) \
if (r[i] != (pred[i] ? (FLOAT_TYPE) a[i] : b[i])) \
__builtin_abort (); \
}
int main ()
{
TEST_ALL (TEST_LOOP)
return 0;
}
gcc/testsuite/gcc.target/aarch64/sve/cond_convert_2.c 0 → 100644
/* { dg-do compile } */
/* { dg-options "-O2 -ftree-vectorize -fno-trapping-math" } */
#include <stdint.h>
#define DEF_LOOP(FLOAT_TYPE, INT_TYPE) \
void __attribute__ ((noipa)) \
test_##INT_TYPE (FLOAT_TYPE *__restrict r, \
INT_TYPE *__restrict a, \
INT_TYPE *__restrict pred, int n) \
{ \
for (int i = 0; i < n; ++i) \
r[i] = pred[i] ? (FLOAT_TYPE) a[i] : 1.0; \
}
#define TEST_ALL(T) \
T (_Float16, int16_t) \
T (_Float16, uint16_t) \
T (float, int32_t) \
T (float, uint32_t) \
T (double, int64_t) \
T (double, uint64_t)
TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {\tscvtf\tz[0-9]+\.h, p[0-7]/m,} 1 } } */
/* { dg-final { scan-assembler-times {\tucvtf\tz[0-9]+\.h, p[0-7]/m,} 1 } } */
/* { dg-final { scan-assembler-times {\tscvtf\tz[0-9]+\.s, p[0-7]/m,} 1 } } */
/* { dg-final { scan-assembler-times {\tucvtf\tz[0-9]+\.s, p[0-7]/m,} 1 } } */
/* { dg-final { scan-assembler-times {\tscvtf\tz[0-9]+\.d, p[0-7]/m,} 1 } } */
/* { dg-final { scan-assembler-times {\tucvtf\tz[0-9]+\.d, p[0-7]/m,} 1 } } */
/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+, z[0-9]+\n} 6 } } */
/* { dg-final { scan-assembler-not {\tmov\tz[^\n]*z} } } */
/* { dg-final { scan-assembler-not {\tsel\t} } } */
gcc/testsuite/gcc.target/aarch64/sve/cond_convert_2_run.c 0 → 100644
/* { dg-do run { target { aarch64_sve_hw } } } */
/* { dg-options "-O2 -ftree-vectorize -ftrapping-math" } */
#include "cond_convert_2.c"
#define N 99
#define TEST_LOOP(FLOAT_TYPE, INT_TYPE) \
{ \
FLOAT_TYPE r[N]; \
INT_TYPE a[N], pred[N]; \
for (int i = 0; i < N; ++i) \
{ \
a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : -1); \
pred[i] = (i % 7 < 4); \
asm volatile ("" ::: "memory"); \
} \
test_##INT_TYPE (r, a, pred, N); \
for (int i = 0; i < N; ++i) \
if (r[i] != (pred[i] ? (FLOAT_TYPE) a[i] : 1.0)) \
__builtin_abort (); \
}
int main ()
{
TEST_ALL (TEST_LOOP)
return 0;
}
gcc/testsuite/gcc.target/aarch64/sve/cond_convert_3.c 0 → 100644
/* { dg-do compile } */
/* { dg-options "-O2 -ftree-vectorize -fno-trapping-math" } */
#include <stdint.h>
#define DEF_LOOP(FLOAT_TYPE, INT_TYPE) \
void __attribute__ ((noipa)) \
test_##INT_TYPE (FLOAT_TYPE *__restrict r, \
INT_TYPE *__restrict a, \
INT_TYPE *__restrict pred, int n) \
{ \
for (int i = 0; i < n; ++i) \
r[i] = pred[i] ? (FLOAT_TYPE) a[i] : 0.0; \
}
#define TEST_ALL(T) \
T (_Float16, int16_t) \
T (_Float16, uint16_t) \
T (float, int32_t) \
T (float, uint32_t) \
T (double, int64_t) \
T (double, uint64_t)
TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {\tscvtf\tz[0-9]+\.h, p[0-7]/m,} 1 } } */
/* { dg-final { scan-assembler-times {\tucvtf\tz[0-9]+\.h, p[0-7]/m,} 1 } } */
/* { dg-final { scan-assembler-times {\tscvtf\tz[0-9]+\.s, p[0-7]/m,} 1 } } */
/* { dg-final { scan-assembler-times {\tucvtf\tz[0-9]+\.s, p[0-7]/m,} 1 } } */
/* { dg-final { scan-assembler-times {\tscvtf\tz[0-9]+\.d, p[0-7]/m,} 1 } } */
/* { dg-final { scan-assembler-times {\tucvtf\tz[0-9]+\.d, p[0-7]/m,} 1 } } */
/* Really we should be able to use MOVPRFX /z here, but at the moment
we're relying on combine to merge a SEL and an arithmetic operation,
and the SEL doesn't allow the "false" value to be zero when the "true"
value is a register. */
/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+, z[0-9]+\n} 6 } } */
/* { dg-final { scan-assembler-not {\tmov\tz[^\n]*z} } } */
/* { dg-final { scan-assembler-not {\tsel\t} } } */
gcc/testsuite/gcc.target/aarch64/sve/cond_convert_3_run.c 0 → 100644
/* { dg-do run { target { aarch64_sve_hw } } } */
/* { dg-options "-O2 -ftree-vectorize -ftrapping-math" } */
#include "cond_convert_3.c"
#define N 99
#define TEST_LOOP(FLOAT_TYPE, INT_TYPE) \
{ \
FLOAT_TYPE r[N]; \
INT_TYPE a[N], pred[N]; \
for (int i = 0; i < N; ++i) \
{ \
a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : -1); \
pred[i] = (i % 7 < 4); \
asm volatile ("" ::: "memory"); \
} \
test_##INT_TYPE (r, a, pred, N); \
for (int i = 0; i < N; ++i) \
if (r[i] != (pred[i] ? (FLOAT_TYPE) a[i] : 0.0)) \
__builtin_abort (); \
}
int main ()
{
TEST_ALL (TEST_LOOP)
return 0;
}
gcc/testsuite/gcc.target/aarch64/sve/cond_convert_4.c 0 → 100644
/* { dg-do compile } */
/* { dg-options "-O2 -ftree-vectorize -fno-trapping-math" } */
#include <stdint.h>
#define DEF_LOOP(FLOAT_TYPE, INT_TYPE) \
void __attribute__ ((noipa)) \
test_##INT_TYPE (INT_TYPE *__restrict r, \
FLOAT_TYPE *__restrict a, \
INT_TYPE *__restrict b, \
INT_TYPE *__restrict pred, int n) \
{ \
for (int i = 0; i < n; ++i) \
r[i] = pred[i] ? (INT_TYPE) a[i] : b[i]; \
}
#define TEST_ALL(T) \
T (_Float16, int16_t) \
T (_Float16, uint16_t) \
T (float, int32_t) \
T (float, uint32_t) \
T (double, int64_t) \
T (double, uint64_t)
TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {\tfcvtzs\tz[0-9]+\.h, p[0-7]/m,} 1 } } */
/* { dg-final { scan-assembler-times {\tfcvtzu\tz[0-9]+\.h, p[0-7]/m,} 1 } } */
/* { dg-final { scan-assembler-times {\tfcvtzs\tz[0-9]+\.s, p[0-7]/m,} 1 } } */
/* { dg-final { scan-assembler-times {\tfcvtzu\tz[0-9]+\.s, p[0-7]/m,} 1 } } */
/* { dg-final { scan-assembler-times {\tfcvtzs\tz[0-9]+\.d, p[0-7]/m,} 1 } } */
/* { dg-final { scan-assembler-times {\tfcvtzu\tz[0-9]+\.d, p[0-7]/m,} 1 } } */
/* { dg-final { scan-assembler-not {\tmov\tz} } } */
/* At the moment we don't manage to avoid using MOVPRFX. */
/* { dg-final { scan-assembler-not {\tmovprfx\t} { xfail *-*-* } } } */
/* { dg-final { scan-assembler-not {\tsel\t} } } */
gcc/testsuite/gcc.target/aarch64/sve/cond_convert_4_run.c 0 → 100644
/* { dg-do run { target { aarch64_sve_hw } } } */
/* { dg-options "-O2 -ftree-vectorize -ftrapping-math" } */
#include "cond_convert_4.c"
#define N 99
#define TEST_LOOP(FLOAT_TYPE, INT_TYPE) \
{ \
INT_TYPE r[N], b[N], pred[N]; \
FLOAT_TYPE a[N]; \
for (int i = 0; i < N; ++i) \
{ \
a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : -1); \
b[i] = (i % 9) * (i % 7 + 1); \
pred[i] = (i % 7 < 4); \
asm volatile ("" ::: "memory"); \
} \
test_##INT_TYPE (r, a, b, pred, N); \
for (int i = 0; i < N; ++i) \
if (r[i] != (pred[i] ? (INT_TYPE) a[i] : b[i])) \
__builtin_abort (); \
}
int main ()
{
TEST_ALL (TEST_LOOP)
return 0;
}
gcc/testsuite/gcc.target/aarch64/sve/cond_convert_5.c 0 → 100644
/* { dg-do compile } */
/* { dg-options "-O2 -ftree-vectorize -fno-trapping-math" } */
#include <stdint.h>
#define DEF_LOOP(FLOAT_TYPE, INT_TYPE) \
void __attribute__ ((noipa)) \
test_##INT_TYPE (INT_TYPE *__restrict r, \
FLOAT_TYPE *__restrict a, \
INT_TYPE *__restrict pred, int n) \
{ \
for (int i = 0; i < n; ++i) \
r[i] = pred[i] ? (INT_TYPE) a[i] : 72; \
}
#define TEST_ALL(T) \
T (_Float16, int16_t) \
T (_Float16, uint16_t) \
T (float, int32_t) \
T (float, uint32_t) \
T (double, int64_t) \
T (double, uint64_t)
TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {\tfcvtzs\tz[0-9]+\.h, p[0-7]/m,} 1 } } */
/* { dg-final { scan-assembler-times {\tfcvtzu\tz[0-9]+\.h, p[0-7]/m,} 1 } } */
/* { dg-final { scan-assembler-times {\tfcvtzs\tz[0-9]+\.s, p[0-7]/m,} 1 } } */
/* { dg-final { scan-assembler-times {\tfcvtzu\tz[0-9]+\.s, p[0-7]/m,} 1 } } */
/* { dg-final { scan-assembler-times {\tfcvtzs\tz[0-9]+\.d, p[0-7]/m,} 1 } } */
/* { dg-final { scan-assembler-times {\tfcvtzu\tz[0-9]+\.d, p[0-7]/m,} 1 } } */
/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+, z[0-9]+\n} 6 } } */
/* { dg-final { scan-assembler-not {\tmov\tz[^\n]*z} } } */
/* { dg-final { scan-assembler-not {\tsel\t} } } */
gcc/testsuite/gcc.target/aarch64/sve/cond_convert_5_run.c 0 → 100644
/* { dg-do run { target { aarch64_sve_hw } } } */
/* { dg-options "-O2 -ftree-vectorize -ftrapping-math" } */
#include "cond_convert_5.c"
#define N 99
#define TEST_LOOP(FLOAT_TYPE, INT_TYPE) \
{ \
INT_TYPE r[N], pred[N]; \
FLOAT_TYPE a[N]; \
for (int i = 0; i < N; ++i) \
{ \
a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : -1); \
pred[i] = (i % 7 < 4); \
asm volatile ("" ::: "memory"); \
} \
test_##INT_TYPE (r, a, pred, N); \
for (int i = 0; i < N; ++i) \
if (r[i] != (pred[i] ? (INT_TYPE) a[i] : 72)) \
__builtin_abort (); \
}
int main ()
{
TEST_ALL (TEST_LOOP)
return 0;
}
gcc/testsuite/gcc.target/aarch64/sve/cond_convert_6.c 0 → 100644
/* { dg-do compile } */
/* { dg-options "-O2 -ftree-vectorize -fno-trapping-math" } */
#include <stdint.h>
#define DEF_LOOP(FLOAT_TYPE, INT_TYPE) \
void __attribute__ ((noipa)) \
test_##INT_TYPE (INT_TYPE *__restrict r, \
FLOAT_TYPE *__restrict a, \
INT_TYPE *__restrict pred, int n) \
{ \
for (int i = 0; i < n; ++i) \
r[i] = pred[i] ? (INT_TYPE) a[i] : 0; \
}
#define TEST_ALL(T) \
T (_Float16, int16_t) \
T (_Float16, uint16_t) \
T (float, int32_t) \
T (float, uint32_t) \
T (double, int64_t) \
T (double, uint64_t)
TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {\tfcvtzs\tz[0-9]+\.h, p[0-7]/m,} 1 } } */
/* { dg-final { scan-assembler-times {\tfcvtzu\tz[0-9]+\.h, p[0-7]/m,} 1 } } */
/* { dg-final { scan-assembler-times {\tfcvtzs\tz[0-9]+\.s, p[0-7]/m,} 1 } } */
/* { dg-final { scan-assembler-times {\tfcvtzu\tz[0-9]+\.s, p[0-7]/m,} 1 } } */
/* { dg-final { scan-assembler-times {\tfcvtzs\tz[0-9]+\.d, p[0-7]/m,} 1 } } */
/* { dg-final { scan-assembler-times {\tfcvtzu\tz[0-9]+\.d, p[0-7]/m,} 1 } } */
/* Really we should be able to use MOVPRFX /z here, but at the moment
we're relying on combine to merge a SEL and an arithmetic operation,
and the SEL doesn't allow the "false" value to be zero when the "true"
value is a register. */
/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+, z[0-9]+\n} 6 } } */
/* { dg-final { scan-assembler-not {\tmov\tz[^\n]*z} } } */
/* { dg-final { scan-assembler-not {\tsel\t} } } */
gcc/testsuite/gcc.target/aarch64/sve/cond_convert_6_run.c 0 → 100644
/* { dg-do run { target { aarch64_sve_hw } } } */
/* { dg-options "-O2 -ftree-vectorize -ftrapping-math" } */
#include "cond_convert_6.c"
#define N 99
#define TEST_LOOP(FLOAT_TYPE, INT_TYPE) \
{ \
INT_TYPE r[N], pred[N]; \
FLOAT_TYPE a[N]; \
for (int i = 0; i < N; ++i) \
{ \
a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : -1); \
pred[i] = (i % 7 < 4); \
asm volatile ("" ::: "memory"); \
} \
test_##INT_TYPE (r, a, pred, N); \
for (int i = 0; i < N; ++i) \
if (r[i] != (pred[i] ? (INT_TYPE) a[i] : 0)) \
__builtin_abort (); \
}
int main ()
{
TEST_ALL (TEST_LOOP)
return 0;
}
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment