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Commit c5cb5d18 by Richard Sandiford Committed by Richard Sandiford
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mips-protos.h (mips_split_const_insns): Declare. 

gcc/
	* config/mips/mips-protos.h (mips_split_const_insns): Declare.
	* config/mips/mips.c (mips_split_const_insns): New function.
	* config/mips/mips.md (move_type): New attribute.
	(mode): Move attribute definition earlier in file.  Add "TI"
	and "TF".
	(dword_mode): New attribute.
	(type): Avoid long line.  Map "move_type"s to "type"s,
	choosing "multi" for doubleword moves if appropriate.
	Swap MTC/MFC comments to match their declaration order.
	(extended_mips16): Default to "yes" if "move_type" is "sll0",
	"type" is "branch" or "jal" is "direct".
	(length): Handle "extended_mips16" first.  Make the default
	"0" for "ghost" instructions.  Set the length from "move_type".
	(truncdisi2, truncdihi2, truncdiqi2): Use "move_type" instead
	of "type", with "sll0" for the register alternative.  Remove the
	"extended_mips16" attribute.
	(zero_extendsidi2, *clear_upper32): Use "move_type" instead
	of "type", with "shift_shift" for the register alternative.
	Remove the "length" attribute.
	(*extend<SHORT:mode><GPR:mode>2, *extendqihi2): Likewise.
	(*zero_extend<SHORT:mode><GPR:mode>2): Use "move_type" instead
	of "type", with "andi" for the register alternative.
	(*zero_extendqihi2): Likewise.
	(*zero_extend<SHORT:mode><GPR:mode>2_mips16e): Use a "move_type"
	of "andi" instead of a "type" of "arith".
	(*zero_extend<SHORT:mode><GPR:mode>2_mips16): Use "move_type"
	instead of "type".
	(*zero_extendqihi2_mips16, mov_<load>l, mov_<load>r, mov_<store>l)
	(mov_<store>r, *mov<mode>_ra): Likewise.
	(extendsidi2): Use "move_type" instead of "type", with "move"
	for the register alternative.
	(*extend<SHORT:mode><GPR:mode>2_mips16e): Use "move_type" instead
	of "type", with "signext" for the register alternative.
	(*extend<SHORT:mode><GPR:mode>2_se<SHORT:size>): Likewise.
	(*extendqihi2_mips16e, *extendqihi2_seb): Likewise.
	(fix_truncdfsi2_insn, fix_truncsfsi2_insn, fix_truncdfdi2)
	(fix_truncsfdi2, floatsidf2, floatdidf2, floatsisf2, floatdisf2)
	(floatdisf2, *branch_equality<mode>_mips16): Likewise.
	(unnamed branch insn): Likewise.
	(*movdi_gp32_fp64): Fold into...
	(*movdi_32bit): ...here.
	(*movdf_hardfloat_64bit, *movdf_hardfloat_32bit): Combine into...
	(*movdf_hardfloat): ...this new pattern.
	(*movdf_softfloat): Remove redundant FPR alternatives.
	(*movti, *movti_mips16, *movtf, *movtf_mips16): Add "mode" attributes.
	(*movv2sf_hardfloat_64bit, *movv2sf_hardfloat_32bit): Combine into...
	(*movv2sf): ...this new pattern.  Use "DF" rather than "SF" for
	the "move" attribute.
	(*movdi_32bit): Use "move_type" instead of "type" and remove the
	"length" attribute.  Use "fpload" and "fpstore" instead of "load"
	and "store" for COP loads and stores.
	(*movdi_32bit_mips16, *movdi_64bit, *movsi_internal, movcc)
	(*movhi_internal, *movhi_mips16, *movqi_internal, *movqi_mips16)
	(*movsf_hardfloat, *movsf_softfloat, *movsi_mips16, *movdf_hardfloat)
	(*movdf_softfloat, *movdf_mips16, *movti, *movti_mips16, *movtf)
	(*movtf_mips16, *movv2sf): Likewise.
	(mfhi<GPR:mode>_<HILO:mode>, mflo<GPR:mode>_<HILO:mode>)
	(load_low<mode>, load_high<mode>, store_word<mode>, mthc1<mode>)
	(mfhc1<mode>): Use "move_type" instead of "move".
	(*low<mode>_mips16): Use "extended_mips16" instead of "length".
	(loadgp_blockage): Remove the "length" attribute.
	(blockage, set_got_version, update_got_version): Likewise.
	(call_internal): Remove the "extended_mips16" attribute.
	(call_value_internal, call_value_multiple_internal): Likewise.
	* config/mips/loongson.md (mov<mode>_internal): Use "move_type"
	instead of "move".
	* config/mips/mips-dsp.md (mips_lbux, mips_lhx, mips_lwx): Remove
	the "length" attribute.

From-SVN: r137194
parent 7d71283c
Showing with 91 additions and 7 deletions
gcc/ChangeLog
2008-06-27 Richard Sandiford <rdsandiford@googlemail.com>
* config/mips/mips-protos.h (mips_split_const_insns): Declare.
* config/mips/mips.c (mips_split_const_insns): New function.
* config/mips/mips.md (move_type): New attribute.
(mode): Move attribute definition earlier in file. Add "TI"
and "TF".
(dword_mode): New attribute.
(type): Avoid long line. Map "move_type"s to "type"s,
choosing "multi" for doubleword moves if appropriate.
Swap MTC/MFC comments to match their declaration order.
(extended_mips16): Default to "yes" if "move_type" is "sll0",
"type" is "branch" or "jal" is "direct".
(length): Handle "extended_mips16" first. Make the default
"0" for "ghost" instructions. Set the length from "move_type".
(truncdisi2, truncdihi2, truncdiqi2): Use "move_type" instead
of "type", with "sll0" for the register alternative. Remove the
"extended_mips16" attribute.
(zero_extendsidi2, *clear_upper32): Use "move_type" instead
of "type", with "shift_shift" for the register alternative.
Remove the "length" attribute.
(*extend<SHORT:mode><GPR:mode>2, *extendqihi2): Likewise.
(*zero_extend<SHORT:mode><GPR:mode>2): Use "move_type" instead
of "type", with "andi" for the register alternative.
(*zero_extendqihi2): Likewise.
(*zero_extend<SHORT:mode><GPR:mode>2_mips16e): Use a "move_type"
of "andi" instead of a "type" of "arith".
(*zero_extend<SHORT:mode><GPR:mode>2_mips16): Use "move_type"
instead of "type".
(*zero_extendqihi2_mips16, mov_<load>l, mov_<load>r, mov_<store>l)
(mov_<store>r, *mov<mode>_ra): Likewise.
(extendsidi2): Use "move_type" instead of "type", with "move"
for the register alternative.
(*extend<SHORT:mode><GPR:mode>2_mips16e): Use "move_type" instead
of "type", with "signext" for the register alternative.
(*extend<SHORT:mode><GPR:mode>2_se<SHORT:size>): Likewise.
(*extendqihi2_mips16e, *extendqihi2_seb): Likewise.
(fix_truncdfsi2_insn, fix_truncsfsi2_insn, fix_truncdfdi2)
(fix_truncsfdi2, floatsidf2, floatdidf2, floatsisf2, floatdisf2)
(floatdisf2, *branch_equality<mode>_mips16): Likewise.
(unnamed branch insn): Likewise.
(*movdi_gp32_fp64): Fold into...
(*movdi_32bit): ...here.
(*movdf_hardfloat_64bit, *movdf_hardfloat_32bit): Combine into...
(*movdf_hardfloat): ...this new pattern.
(*movdf_softfloat): Remove redundant FPR alternatives.
(*movti, *movti_mips16, *movtf, *movtf_mips16): Add "mode" attributes.
(*movv2sf_hardfloat_64bit, *movv2sf_hardfloat_32bit): Combine into...
(*movv2sf): ...this new pattern. Use "DF" rather than "SF" for
the "move" attribute.
(*movdi_32bit): Use "move_type" instead of "type" and remove the
"length" attribute. Use "fpload" and "fpstore" instead of "load"
and "store" for COP loads and stores.
(*movdi_32bit_mips16, *movdi_64bit, *movsi_internal, movcc)
(*movhi_internal, *movhi_mips16, *movqi_internal, *movqi_mips16)
(*movsf_hardfloat, *movsf_softfloat, *movsi_mips16, *movdf_hardfloat)
(*movdf_softfloat, *movdf_mips16, *movti, *movti_mips16, *movtf)
(*movtf_mips16, *movv2sf): Likewise.
(mfhi<GPR:mode>_<HILO:mode>, mflo<GPR:mode>_<HILO:mode>)
(load_low<mode>, load_high<mode>, store_word<mode>, mthc1<mode>)
(mfhc1<mode>): Use "move_type" instead of "move".
(*low<mode>_mips16): Use "extended_mips16" instead of "length".
(loadgp_blockage): Remove the "length" attribute.
(blockage, set_got_version, update_got_version): Likewise.
(call_internal): Remove the "extended_mips16" attribute.
(call_value_internal, call_value_multiple_internal): Likewise.
* config/mips/loongson.md (mov<mode>_internal): Use "move_type"
instead of "move".
* config/mips/mips-dsp.md (mips_lbux, mips_lhx, mips_lwx): Remove
the "length" attribute.
2008-06-27 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
* c-format.c (handle_format_attribute): Fix -Wc++-compat and/or
......
gcc/config/mips/loongson.md
......@@ -83,7 +83,7 @@
(match_operand:VWHB 1 "move_operand" "f,m,f,dYG,dYG,dYG,m"))]
"TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
{ return mips_output_move (operands[0], operands[1]); }
[(set_attr "type" "fpstore,fpload,mfc,mtc,move,store,load")
[(set_attr "move_type" "fpstore,fpload,mfc,mtc,move,store,load")
(set_attr "mode" "DI")])
;; Initialization of a vector.
......
gcc/config/mips/mips-dsp.md
......@@ -1017,8 +1017,7 @@
"ISA_HAS_DSP"
"lbux\t%0,%2(%1)"
[(set_attr "type" "load")
(set_attr "mode" "SI")
(set_attr "length" "4")])
(set_attr "mode" "SI")])
(define_insn "mips_lhx"
[(set (match_operand:SI 0 "register_operand" "=d")
......@@ -1029,8 +1028,7 @@
"ISA_HAS_DSP"
"lhx\t%0,%2(%1)"
[(set_attr "type" "load")
(set_attr "mode" "SI")
(set_attr "length" "4")])
(set_attr "mode" "SI")])
(define_insn "mips_lwx"
[(set (match_operand:SI 0 "register_operand" "=d")
......@@ -1039,8 +1037,7 @@
"ISA_HAS_DSP"
"lwx\t%0,%2(%1)"
[(set_attr "type" "load")
(set_attr "mode" "SI")
(set_attr "length" "4")])
(set_attr "mode" "SI")])
;; Table 2-8. MIPS DSP ASE Instructions: Branch
;; BPOSGE32
......
gcc/config/mips/mips-protos.h
......@@ -171,6 +171,7 @@ extern bool mips_legitimate_address_p (enum machine_mode, rtx, bool);
extern bool mips_stack_address_p (rtx, enum machine_mode);
extern int mips_address_insns (rtx, enum machine_mode, bool);
extern int mips_const_insns (rtx);
extern int mips_split_const_insns (rtx);
extern int mips_load_store_insns (rtx, rtx);
extern int mips_idiv_insns (void);
extern rtx mips_emit_move (rtx, rtx);
......
gcc/config/mips/mips.c
......@@ -2121,6 +2121,21 @@ mips_const_insns (rtx x)
}
}
/* X is a doubleword constant that can be handled by splitting it into
two words and loading each word separately. Return the number of
instructions required to do this. */
int
mips_split_const_insns (rtx x)
{
unsigned int low, high;
low = mips_const_insns (mips_subword (x, false));
high = mips_const_insns (mips_subword (x, true));
gcc_assert (low > 0 && high > 0);
return low + high;
}
/* Return the number of instructions needed to implement INSN,
given that it loads from or stores to MEM. Count extended
MIPS16 instructions as two instructions. */
......
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