Commit c5c2ca16 by Stephane Carrez Committed by Stephane Carrez

larith.asm (L_regs_frame): New for _.frame.

	* config/m68hc11/larith.asm (L_regs_frame): New for _.frame.
	Put the soft registers in bss for 68HC12.
	(L_regs_d3_4): New for _.d3 and _.d4.
	(L_regs_d5_6): Likewise.
	(L_regs_d1_2): Likewise.
	* config/m68hc11/t-m68hc11-gas (T_CPPFLAGS): Compile new parts.

From-SVN: r41846
parent 62aa6b06
2001-05-04 Stephane Carrez <Stephane.Carrez@worldnet.fr> 2001-05-04 Stephane Carrez <Stephane.Carrez@worldnet.fr>
* config/m68hc11/larith.asm (L_regs_frame): New for _.frame.
Put the soft registers in bss for 68HC12.
(L_regs_d3_4): New for _.d3 and _.d4.
(L_regs_d5_6): Likewise.
(L_regs_d1_2): Likewise.
* config/m68hc11/t-m68hc11-gas (T_CPPFLAGS): Compile new parts.
2001-05-04 Stephane Carrez <Stephane.Carrez@worldnet.fr>
* config/m68hc11/m68hc11.h (CPP_SPEC): Pass -D__HAVE_SHORT_DOUBLE__ * config/m68hc11/m68hc11.h (CPP_SPEC): Pass -D__HAVE_SHORT_DOUBLE__
to the pre-processor when -fshort-double is specified. to the pre-processor when -fshort-double is specified.
* config/m68hc11/m68hc11.2 (CPP_SPEC): Likewise. * config/m68hc11/m68hc11.2 (CPP_SPEC): Likewise.
......
...@@ -52,38 +52,69 @@ NAME: .word 0; \ ...@@ -52,38 +52,69 @@ NAME: .word 0; \
#else #else
.sect .page0 .sect .page0
#endif #endif
.globl _.tmp,_.frame .globl _.tmp
.globl _.z,_.xy .globl _.z,_.xy
REG(_.tmp) REG(_.tmp)
REG(_.z) REG(_.z)
REG(_.xy) REG(_.xy)
REG(_.frame)
#endif #endif
#ifdef L_regs_d1_8 #ifdef L_regs_frame
/* Pseudo hard registers used by gcc.
They must be located in page0.
They will normally appear at the end of .page0 section. */
#ifdef mc68hc12 #ifdef mc68hc12
.sect .bss .sect .bss
#else #else
.sect .page0 .sect .page0
#endif #endif
.globl _.d1,_.d2,_.d3,_.d4,_.d5,_.d6 .globl _.frame
.globl _.d7,_.d8 REG(_.frame)
#endif
#ifdef L_regs_d1_2
#ifdef mc68hc12
.sect .bss
#else
.sect .page0
#endif
.globl _.d1,_.d2
REG(_.d1) REG(_.d1)
REG(_.d2) REG(_.d2)
#endif
#ifdef L_regs_d3_4
#ifdef mc68hc12
.sect .bss
#else
.sect .page0
#endif
.globl _.d3,_.d4
REG(_.d3) REG(_.d3)
REG(_.d4) REG(_.d4)
#endif
#ifdef L_regs_d5_6
#ifdef mc68hc12
.sect .bss
#else
.sect .page0
#endif
.globl _.d5,_.d6
REG(_.d5) REG(_.d5)
REG(_.d6) REG(_.d6)
#endif
#ifdef L_regs_d7_8
#ifdef mc68hc12
.sect .bss
#else
.sect .page0
#endif
.globl _.d7,_.d8
REG(_.d7) REG(_.d7)
REG(_.d8) REG(_.d8)
#endif #endif
#ifdef L_regs_d8_16 #ifdef L_regs_d9_16
/* Pseudo hard registers used by gcc. /* Pseudo hard registers used by gcc.
They must be located in page0. They must be located in page0.
They will normally appear at the end of .page0 section. */ They will normally appear at the end of .page0 section. */
......
...@@ -21,7 +21,8 @@ LIB1ASMFUNCS = _mulsi3 \ ...@@ -21,7 +21,8 @@ LIB1ASMFUNCS = _mulsi3 \
_mulqi3 _ashlsi3 _ashrsi3 _lshrsi3 \ _mulqi3 _ashlsi3 _ashrsi3 _lshrsi3 \
_divmodhi4 _mulhi3 _mulhi32 \ _divmodhi4 _mulhi3 _mulhi32 \
_memcpy _memset _negsi2 _one_cmplsi2 \ _memcpy _memset _negsi2 _one_cmplsi2 \
_regs_min _regs_d1_8 _regs_d8_16 _regs_d17_32 \ _regs_min _regs_frame _regs_d1_2 \
_regs_d3_4 _regs_d5_6 _regs_d7_8 _regs_d9_16 _regs_d17_32 \
_premain __exit _abort _cleanup \ _premain __exit _abort _cleanup \
_adddi3 _subdi3 _notdi2 \ _adddi3 _subdi3 _notdi2 \
_ashrhi3 _lshrhi3 _lshlhi3 _ashrqi3 _lshlqi3 _map_data _init_bss _ashrhi3 _lshrhi3 _lshlhi3 _ashrqi3 _lshlqi3 _map_data _init_bss
......
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