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Commit c4b50f1a by Richard Henderson Committed by Richard Henderson
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alpha.c (mode_mask_operand): Simplify without ifdefs. 

        * config/alpha/alpha.c (mode_mask_operand): Simplify without ifdefs.
        (print_operand) ['U']: Likewise.
        (alpha_expand_unaligned_store): Correct constants for 32-bit cross.
        (alpha_expand_unaligned_store_words): Likewise.
        (alpha_expand_builtin_vector_binop): Fix typo.
        (enum alpha_builtin, code_for_builtin): Add remaining ext, ins, msk,
        umulh, and cix insns.
        (one_arg_builtins): Add cix builtins.
        (two_arg_builtins): Add ext, ins, msk, umulh builtins.
        (alpha_expand_builtin): Fix typo in arity.
        * config/alpha/alpha.md (UNSPEC_CTLZ, UNSPEC_CTPOP): New.
        (builtin_extbl, builtin_extwl, builtin_extll, builtin_extwh,
        builtin_extlh, builtin_insbl, builtin_inswl, builtin_insll,
        builtin_insql, builtin_inswh, builtin_inslh, builtin_insqh,
        builtin_mskbl, builtin_mskwl, builtin_mskll, builtin_mskql,
        builtin_mskwh, builtin_msklh, builtin_mskqh, builtin_cttz,
        builtin_ctlz, builtin_ctpop): New.
        * doc/extend.texi (Alpha Built-in Functions): Update.

        * gcc.dg/alpha-base-1.c: Add ext/ins/msk/umulh cases.
        * gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: Use -mcpu=ev67.
        * gcc.dg/alpha-cix-1.c, gcc.dg/alpha-cix-2.c: New.

From-SVN: r54267
parent afb0f770
Showing with 561 additions and 94 deletions
gcc/ChangeLog
2002-06-04 Richard Henderson <rth@redhat.com>
* config/alpha/alpha.c (mode_mask_operand): Simplify without ifdefs.
(print_operand) ['U']: Likewise.
(alpha_expand_unaligned_store): Correct constants for 32-bit cross.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_builtin_vector_binop): Fix typo.
(enum alpha_builtin, code_for_builtin): Add remaining ext, ins, msk,
umulh, and cix insns.
(one_arg_builtins): Add cix builtins.
(two_arg_builtins): Add ext, ins, msk, umulh builtins.
(alpha_expand_builtin): Fix typo in arity.
* config/alpha/alpha.md (UNSPEC_CTLZ, UNSPEC_CTPOP): New.
(builtin_extbl, builtin_extwl, builtin_extll, builtin_extwh,
builtin_extlh, builtin_insbl, builtin_inswl, builtin_insll,
builtin_insql, builtin_inswh, builtin_inslh, builtin_insqh,
builtin_mskbl, builtin_mskwl, builtin_mskll, builtin_mskql,
builtin_mskwh, builtin_msklh, builtin_mskqh, builtin_cttz,
builtin_ctlz, builtin_ctpop): New.
* doc/extend.texi (Alpha Built-in Functions): Update.
2002-06-04 Geoffrey Keating <geoffk@redhat.com>
* gengtype.c (write_gc_root): Don't unnecessarily prevent
......
gcc/config/alpha/alpha.md
......@@ -56,6 +56,8 @@
(UNSPEC_AMASK 24)
(UNSPEC_IMPLVER 25)
(UNSPEC_PERR 26)
(UNSPEC_CTLZ 27)
(UNSPEC_CTPOP 28)
])
;; UNSPEC_VOLATILE:
......@@ -6990,6 +6992,51 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
;; actually differentiate between ILOG and ICMP in the schedule.
[(set_attr "type" "icmp")])
(define_expand "builtin_extbl"
[(match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "reg_or_0_operand" "")
(match_operand:DI 2 "reg_or_8bit_operand" "")]
""
{
rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
if (WORDS_BIG_ENDIAN)
gen = gen_extxl_be;
else
gen = gen_extxl_le;
emit_insn ((*gen) (operands[0], operands[1], GEN_INT (8), operands[2]));
DONE;
})
(define_expand "builtin_extwl"
[(match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "reg_or_0_operand" "")
(match_operand:DI 2 "reg_or_8bit_operand" "")]
""
{
rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
if (WORDS_BIG_ENDIAN)
gen = gen_extxl_be;
else
gen = gen_extxl_le;
emit_insn ((*gen) (operands[0], operands[1], GEN_INT (16), operands[2]));
DONE;
})
(define_expand "builtin_extll"
[(match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "reg_or_0_operand" "")
(match_operand:DI 2 "reg_or_8bit_operand" "")]
""
{
rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
if (WORDS_BIG_ENDIAN)
gen = gen_extxl_be;
else
gen = gen_extxl_le;
emit_insn ((*gen) (operands[0], operands[1], GEN_INT (32), operands[2]));
DONE;
})
(define_expand "builtin_extql"
[(match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "reg_or_0_operand" "")
......@@ -7005,6 +7052,36 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
DONE;
})
(define_expand "builtin_extwh"
[(match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "reg_or_0_operand" "")
(match_operand:DI 2 "reg_or_8bit_operand" "")]
""
{
rtx (*gen) PARAMS ((rtx, rtx, rtx));
if (WORDS_BIG_ENDIAN)
gen = gen_extwh_be;
else
gen = gen_extwh_le;
emit_insn ((*gen) (operands[0], operands[1], operands[2]));
DONE;
})
(define_expand "builtin_extlh"
[(match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "reg_or_0_operand" "")
(match_operand:DI 2 "reg_or_8bit_operand" "")]
""
{
rtx (*gen) PARAMS ((rtx, rtx, rtx));
if (WORDS_BIG_ENDIAN)
gen = gen_extlh_be;
else
gen = gen_extlh_le;
emit_insn ((*gen) (operands[0], operands[1], operands[2]));
DONE;
})
(define_expand "builtin_extqh"
[(match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "reg_or_0_operand" "")
......@@ -7020,6 +7097,198 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
DONE;
})
(define_expand "builtin_insbl"
[(match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "reg_or_0_operand" "")
(match_operand:DI 2 "reg_or_8bit_operand" "")]
""
{
rtx (*gen) PARAMS ((rtx, rtx, rtx));
if (WORDS_BIG_ENDIAN)
gen = gen_insbl_be;
else
gen = gen_insbl_le;
operands[1] = gen_lowpart (QImode, operands[1]);
emit_insn ((*gen) (operands[0], operands[1], operands[2]));
DONE;
})
(define_expand "builtin_inswl"
[(match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "reg_or_0_operand" "")
(match_operand:DI 2 "reg_or_8bit_operand" "")]
""
{
rtx (*gen) PARAMS ((rtx, rtx, rtx));
if (WORDS_BIG_ENDIAN)
gen = gen_inswl_be;
else
gen = gen_inswl_le;
operands[1] = gen_lowpart (HImode, operands[1]);
emit_insn ((*gen) (operands[0], operands[1], operands[2]));
DONE;
})
(define_expand "builtin_insll"
[(match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "reg_or_0_operand" "")
(match_operand:DI 2 "reg_or_8bit_operand" "")]
""
{
rtx (*gen) PARAMS ((rtx, rtx, rtx));
if (WORDS_BIG_ENDIAN)
gen = gen_insll_be;
else
gen = gen_insll_le;
operands[1] = gen_lowpart (SImode, operands[1]);
emit_insn ((*gen) (operands[0], operands[1], operands[2]));
emit_insn ((*gen) (operands[0], operands[1], operands[2]));
DONE;
})
(define_expand "builtin_insql"
[(match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "reg_or_0_operand" "")
(match_operand:DI 2 "reg_or_8bit_operand" "")]
""
{
rtx (*gen) PARAMS ((rtx, rtx, rtx));
if (WORDS_BIG_ENDIAN)
gen = gen_insql_be;
else
gen = gen_insql_le;
emit_insn ((*gen) (operands[0], operands[1], operands[2]));
DONE;
})
(define_expand "builtin_inswh"
[(match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "register_operand" "")
(match_operand:DI 2 "reg_or_8bit_operand" "")]
""
{
emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (16), operands[2]));
DONE;
})
(define_expand "builtin_inslh"
[(match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "register_operand" "")
(match_operand:DI 2 "reg_or_8bit_operand" "")]
""
{
emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (32), operands[2]));
DONE;
})
(define_expand "builtin_insqh"
[(match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "register_operand" "")
(match_operand:DI 2 "reg_or_8bit_operand" "")]
""
{
emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (64), operands[2]));
DONE;
})
(define_expand "builtin_mskbl"
[(match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "reg_or_0_operand" "")
(match_operand:DI 2 "reg_or_8bit_operand" "")]
""
{
rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
rtx mask;
if (WORDS_BIG_ENDIAN)
gen = gen_mskxl_be;
else
gen = gen_mskxl_le;
mask = GEN_INT (0xff);
emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
DONE;
})
(define_expand "builtin_mskwl"
[(match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "reg_or_0_operand" "")
(match_operand:DI 2 "reg_or_8bit_operand" "")]
""
{
rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
rtx mask;
if (WORDS_BIG_ENDIAN)
gen = gen_mskxl_be;
else
gen = gen_mskxl_le;
mask = GEN_INT (0xffff);
emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
DONE;
})
(define_expand "builtin_mskll"
[(match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "reg_or_0_operand" "")
(match_operand:DI 2 "reg_or_8bit_operand" "")]
""
{
rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
rtx mask;
if (WORDS_BIG_ENDIAN)
gen = gen_mskxl_be;
else
gen = gen_mskxl_le;
mask = immed_double_const (0xffffffff, 0, DImode);
emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
DONE;
})
(define_expand "builtin_mskql"
[(match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "reg_or_0_operand" "")
(match_operand:DI 2 "reg_or_8bit_operand" "")]
""
{
rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
rtx mask;
if (WORDS_BIG_ENDIAN)
gen = gen_mskxl_be;
else
gen = gen_mskxl_le;
mask = constm1_rtx;
emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
DONE;
})
(define_expand "builtin_mskwh"
[(match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "register_operand" "")
(match_operand:DI 2 "reg_or_8bit_operand" "")]
""
{
emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (16), operands[2]));
DONE;
})
(define_expand "builtin_msklh"
[(match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "register_operand" "")
(match_operand:DI 2 "reg_or_8bit_operand" "")]
""
{
emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (32), operands[2]));
DONE;
})
(define_expand "builtin_mskqh"
[(match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "register_operand" "")
(match_operand:DI 2 "reg_or_8bit_operand" "")]
""
{
emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (64), operands[2]));
DONE;
})
(define_expand "builtin_zap"
[(set (match_operand:DI 0 "register_operand" "")
(and:DI (unspec:DI
......@@ -7366,6 +7635,29 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
"TARGET_MAX"
"unpkbw %r1,%0"
[(set_attr "type" "mvi")])
(define_expand "builtin_cttz"
[(set (match_operand:DI 0 "register_operand" "")
(unspec:DI [(match_operand:DI 1 "register_operand" "")]
UNSPEC_CTTZ))]
"TARGET_CIX"
"")
(define_insn "builtin_ctlz"
[(set (match_operand:DI 0 "register_operand" "=r")
(unspec:DI [(match_operand:DI 1 "register_operand" "r")]
UNSPEC_CTLZ))]
"TARGET_CIX"
"ctlz %1,%0"
[(set_attr "type" "mvi")])
(define_insn "builtin_ctpop"
[(set (match_operand:DI 0 "register_operand" "=r")
(unspec:DI [(match_operand:DI 1 "register_operand" "r")]
UNSPEC_CTPOP))]
"TARGET_CIX"
"ctpop %1,%0"
[(set_attr "type" "mvi")])
;; The call patterns are at the end of the file because their
;; wildcard operand0 interferes with nice recognition.
......
gcc/doc/extend.texi
......@@ -4773,8 +4773,28 @@ long __builtin_alpha_implver (void)
long __builtin_alpha_rpcc (void)
long __builtin_alpha_amask (long)
long __builtin_alpha_cmpbge (long, long)
long __builtin_alpha_extbl (long, long)
long __builtin_alpha_extwl (long, long)
long __builtin_alpha_extll (long, long)
long __builtin_alpha_extql (long, long)
long __builtin_alpha_extwh (long, long)
long __builtin_alpha_extlh (long, long)
long __builtin_alpha_extqh (long, long)
long __builtin_alpha_insbl (long, long)
long __builtin_alpha_inswl (long, long)
long __builtin_alpha_insll (long, long)
long __builtin_alpha_insql (long, long)
long __builtin_alpha_inswh (long, long)
long __builtin_alpha_inslh (long, long)
long __builtin_alpha_insqh (long, long)
long __builtin_alpha_mskbl (long, long)
long __builtin_alpha_mskwl (long, long)
long __builtin_alpha_mskll (long, long)
long __builtin_alpha_mskql (long, long)
long __builtin_alpha_mskwh (long, long)
long __builtin_alpha_msklh (long, long)
long __builtin_alpha_mskqh (long, long)
long __builtin_alpha_umulh (long, long)
long __builtin_alpha_zap (long, long)
long __builtin_alpha_zapnot (long, long)
@end example
......@@ -4800,6 +4820,17 @@ long __builtin_alpha_maxsw4 (long, long)
long __builtin_alpha_perr (long, long)
@end example
The following built-in functions are always with @option{-mcix}
or @option{-mcpu=@var{cpu}} where @var{cpu} is @code{ev67} or
later. They all generate the machine instruction that is part
of the name.
@example
long __builtin_alpha_cttz (long)
long __builtin_alpha_ctlz (long)
long __builtin_alpha_ctpop (long)
@end example
@node X86 Built-in Functions
@subsection X86 Built-in Functions
......
gcc/testsuite/ChangeLog
2002-06-04 Richard Henderson <rth@redhat.com>
* gcc.dg/alpha-base-1.c: Add ext/ins/msk/umulh cases.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: Use -mcpu=ev67.
* gcc.dg/alpha-cix-1.c, gcc.dg/alpha-cix-2.c: New.
2002-06-04 Aldy Hernandez <aldyh@redhat.com>
* gcc.dg/altivec-2.c: Remove test for invalid vector type V2DF.
......
gcc/testsuite/gcc.dg/alpha-base-1.c
......@@ -15,8 +15,32 @@ void test_BASE (long x, long y)
sink = __builtin_alpha_cmpbge (x, y);
sink = __builtin_alpha_cmpbge (-1, x);
sink = __builtin_alpha_extbl (x, y);
sink = __builtin_alpha_extwl (x, y);
sink = __builtin_alpha_extll (x, y);
sink = __builtin_alpha_extql (x, y);
sink = __builtin_alpha_extwh (x, y);
sink = __builtin_alpha_extlh (x, y);
sink = __builtin_alpha_extqh (x, y);
sink = __builtin_alpha_insbl (x, y);
sink = __builtin_alpha_inswl (x, y);
sink = __builtin_alpha_insll (x, y);
sink = __builtin_alpha_insql (x, y);
sink = __builtin_alpha_inswh (x, y);
sink = __builtin_alpha_inslh (x, y);
sink = __builtin_alpha_insqh (x, y);
sink = __builtin_alpha_mskbl (x, y);
sink = __builtin_alpha_mskwl (x, y);
sink = __builtin_alpha_mskll (x, y);
sink = __builtin_alpha_mskql (x, y);
sink = __builtin_alpha_mskwh (x, y);
sink = __builtin_alpha_msklh (x, y);
sink = __builtin_alpha_mskqh (x, y);
sink = __builtin_alpha_umulh (x, y);
}
void test_zap (long x, long y)
......
gcc/testsuite/gcc.dg/alpha-cix-1.c 0 → 100644
/* Test that the CIX isa builtins compile. */
/* { dg-do link { target alpha*-*-* } } */
/* { dg-options "-mcpu=ev67" } */
void test_CIX (long x)
{
volatile long sink;
sink = __builtin_alpha_cttz (x);
sink = __builtin_alpha_ctlz (x);
sink = __builtin_alpha_ctpop (x);
}
int main() { return 0; }
gcc/testsuite/gcc.dg/alpha-cix-2.c 0 → 100644
/* Test that alpha-cix-1.c compiles with optimization. */
/* { dg-do link { target alpha*-*-* } } */
/* { dg-options "-mcpu=ev67 -O2" } */
#include "alpha-cix-1.c"
gcc/testsuite/gcc.dg/alpha-max-1.c
/* Test that the MAX isa builtins compile. */
/* { dg-do link { target alpha*-*-* } } */
/* { dg-options "-mmax" } */
/* { dg-options "-mcpu=pca56" } */
void test_MAX (long x, long y)
{
......
gcc/testsuite/gcc.dg/alpha-max-2.c
/* Test that alpha-max-1.c compiles with optimization. */
/* { dg-do link { target alpha*-*-* } } */
/* { dg-options "-mmax -O2" } */
/* { dg-options "-mcpu=pca56 -O2" } */
#include "alpha-max-1.c"
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