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lvzhengyang
riscv-gcc-1
Commits
c3de4fe6
Commit
c3de4fe6
authored
May 03, 1992
by
Jim Wilson
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*** empty log message ***
From-SVN: r873
parent
5c18abb4
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Showing
2 changed files
with
21 additions
and
8 deletions
+21
-8
gcc/config/sparc/sparc.c
+5
-2
gcc/sched.c
+16
-6
No files found.
gcc/config/sparc/sparc.c
View file @
c3de4fe6
...
@@ -1090,10 +1090,13 @@ output_move_double (operands)
...
@@ -1090,10 +1090,13 @@ output_move_double (operands)
if it is in a struct. But a DImode need not be 8-byte aligned,
if it is in a struct. But a DImode need not be 8-byte aligned,
because it could be a struct containing two ints or pointers.
because it could be a struct containing two ints or pointers.
Hence, a constant DFmode address will always be 8-byte aligned.
Hence, a constant DFmode address will always be 8-byte aligned.
Any DFmode access inside a struct will always be aligned.
If TARGET_HOPE_ALIGN, then assume all doubles are aligned even if this
If TARGET_HOPE_ALIGN, then assume all doubles are aligned even if this
is not a constant address. */
is not a constant address. */
else
if
(
GET_CODE
(
addr
)
==
MEM
&&
GET_MODE
(
addr
)
==
DFmode
else
if
(
GET_MODE
(
addr
)
==
DFmode
&&
(
CONSTANT_P
(
addr
)
||
TARGET_HOPE_ALIGN
))
&&
(
CONSTANT_P
(
XEXP
(
addr
,
0
))
||
MEM_IN_STRUCT_P
(
addr
)
||
TARGET_HOPE_ALIGN
))
return
(
addr
==
operands
[
1
]
?
"ldd %1,%0"
:
"std %1,%0"
);
return
(
addr
==
operands
[
1
]
?
"ldd %1,%0"
:
"std %1,%0"
);
}
}
...
...
gcc/sched.c
View file @
c3de4fe6
...
@@ -137,6 +137,9 @@ static int *insn_luid;
...
@@ -137,6 +137,9 @@ static int *insn_luid;
static
int
*
insn_priority
;
static
int
*
insn_priority
;
#define INSN_PRIORITY(INSN) (insn_priority[INSN_UID (INSN)])
#define INSN_PRIORITY(INSN) (insn_priority[INSN_UID (INSN)])
static
short
*
insn_costs
;
#define INSN_COST(INSN) insn_costs[INSN_UID (INSN)]
#define DONE_PRIORITY -1
#define DONE_PRIORITY -1
#define MAX_PRIORITY 0x7fffffff
#define MAX_PRIORITY 0x7fffffff
#define TAIL_PRIORITY 0x7ffffffe
#define TAIL_PRIORITY 0x7ffffffe
...
@@ -899,13 +902,19 @@ insn_cost (insn)
...
@@ -899,13 +902,19 @@ insn_cost (insn)
{
{
register
int
cost
;
register
int
cost
;
if
(
INSN_COST
(
insn
))
return
INSN_COST
(
insn
);
recog_memoized
(
insn
);
recog_memoized
(
insn
);
/* A USE insn, or something else we don't need to understand.
/* A USE insn, or something else we don't need to understand.
We can't pass these directly to result_ready_cost because it will trigger
We can't pass these directly to result_ready_cost because it will trigger
a fatal error for unrecognizable insns. */
a fatal error for unrecognizable insns. */
if
(
INSN_CODE
(
insn
)
<
0
)
if
(
INSN_CODE
(
insn
)
<
0
)
return
1
;
{
INSN_COST
(
insn
)
=
1
;
return
1
;
}
else
else
{
{
cost
=
result_ready_cost
(
insn
);
cost
=
result_ready_cost
(
insn
);
...
@@ -913,6 +922,7 @@ insn_cost (insn)
...
@@ -913,6 +922,7 @@ insn_cost (insn)
if
(
cost
<
1
)
if
(
cost
<
1
)
cost
=
1
;
cost
=
1
;
INSN_COST
(
insn
)
=
cost
;
return
cost
;
return
cost
;
}
}
}
}
...
@@ -1422,14 +1432,14 @@ sched_analyze_2 (x, insn)
...
@@ -1422,14 +1432,14 @@ sched_analyze_2 (x, insn)
case
ASM_OPERANDS
:
case
ASM_OPERANDS
:
case
ASM_INPUT
:
case
ASM_INPUT
:
case
UNSPEC_VOLATILE
:
case
UNSPEC_VOLATILE
:
case
TRAP_IF
:
{
{
rtx
u
;
rtx
u
;
/* Traditional and volatile asm instructions must be considered to use
/* Traditional and volatile asm instructions must be considered to use
and clobber all hard registers and all of memory. So must
and clobber all hard registers and all of memory. So must
UNSPEC_VOLATILE operations. */
TRAP_IF and UNSPEC_VOLATILE operations. */
if
((
code
==
ASM_OPERANDS
&&
MEM_VOLATILE_P
(
x
))
||
code
==
ASM_INPUT
if
(
code
!=
ASM_OPERANDS
||
MEM_VOLATILE_P
(
x
))
||
code
==
UNSPEC_VOLATILE
)
{
{
for
(
i
=
0
;
i
<
FIRST_PSEUDO_REGISTER
;
i
++
)
for
(
i
=
0
;
i
<
FIRST_PSEUDO_REGISTER
;
i
++
)
{
{
...
@@ -3794,10 +3804,9 @@ schedule_insns (dump_file)
...
@@ -3794,10 +3804,9 @@ schedule_insns (dump_file)
/* Allocate data for this pass. See comments, above,
/* Allocate data for this pass. See comments, above,
for what these vectors do. */
for what these vectors do. */
/* ??? Instruction splitting below may create new instructions, so these
arrays must be bigger than just max_uid. */
insn_luid
=
(
int
*
)
alloca
(
max_uid
*
sizeof
(
int
));
insn_luid
=
(
int
*
)
alloca
(
max_uid
*
sizeof
(
int
));
insn_priority
=
(
int
*
)
alloca
(
max_uid
*
sizeof
(
int
));
insn_priority
=
(
int
*
)
alloca
(
max_uid
*
sizeof
(
int
));
insn_costs
=
(
short
*
)
alloca
(
max_uid
*
sizeof
(
short
));
insn_ref_count
=
(
int
*
)
alloca
(
max_uid
*
sizeof
(
int
));
insn_ref_count
=
(
int
*
)
alloca
(
max_uid
*
sizeof
(
int
));
if
(
reload_completed
==
0
)
if
(
reload_completed
==
0
)
...
@@ -3848,6 +3857,7 @@ schedule_insns (dump_file)
...
@@ -3848,6 +3857,7 @@ schedule_insns (dump_file)
bzero
(
insn_luid
,
max_uid
*
sizeof
(
int
));
bzero
(
insn_luid
,
max_uid
*
sizeof
(
int
));
bzero
(
insn_priority
,
max_uid
*
sizeof
(
int
));
bzero
(
insn_priority
,
max_uid
*
sizeof
(
int
));
bzero
(
insn_costs
,
max_uid
*
sizeof
(
short
));
bzero
(
insn_ref_count
,
max_uid
*
sizeof
(
int
));
bzero
(
insn_ref_count
,
max_uid
*
sizeof
(
int
));
/* Schedule each basic block, block by block. */
/* Schedule each basic block, block by block. */
...
...
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