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riscv-gcc-1
Commit c329c9bb by Tom Wood
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(length attribute): Branches may be expanded to two instructions by the assembler. 

(length attribute): Branches may be expanded to two
	instructions by the assembler.
	(DFmode bcnd pattern): Don't try to fill the delay slot.
	(CCmode bbx patterns): Reverse the 1/0, not the condition.
(BLKmode load/store patterns): New.
	(call_block_move, call_movstrsi_loop): Allow any mode for the preload.

From-SVN: r2928
parent 23f5bf99
Showing with 97 additions and 40 deletions
gcc/config/m88k/m88k.md
......@@ -2,7 +2,7 @@
;; Copyright (C) 1988, 1989, 1990, 1991 Free Software Foundation, Inc.
;; Contributed by Michael Tiemann (tiemann@mcc.com)
;; Additional changes by Michael Meissner (meissner@osf.org)
;; Currently supported by Tom Wood (wood@dg-rtp.dg.com)
;; Version 2 port by Tom Wood (Tom_Wood@NeXT.com)
;; This file is part of GNU CC.
......@@ -28,7 +28,7 @@
(define_expand "m88k_sccs_id"
[(match_operand:SI 0 "" "")]
""
"{ static char sccs_id[] = \"@(#)m88k.md 2.3.2.2 11/05/92 09:03:51\";
"{ static char sccs_id[] = \"@(#)m88k.md 2.3.3.2 12/16/92 08:26:12\";
FAIL; }")
;; Attribute specifications
......@@ -60,7 +60,7 @@
; Length in # of instructions of each insn. The values are not exact, but
; are safe.
(define_attr "length" ""
(cond [(eq_attr "type" "marith")
(cond [(eq_attr "type" "marith,weird,branch")
(const_int 2)]
(const_int 1)))
......@@ -834,15 +834,16 @@
operands[3] = op2;
}
if (GET_CODE (operands[3]) == LABEL_REF)
return \"bcnd%. 0x5,%1,%3\;bcnd %#ne0,%d1,%3\";
return \"bcnd 0x5,%1,%3\;bcnd %#ne0,%d1,%3\";
operands[3] = gen_label_rtx ();
label_num = XINT (operands[3], 3);
output_asm_insn (\"bcnd%. 0x5,%1,%3\;bcnd %#eq0,%d1,%2\", operands);
output_asm_insn (\"bcnd 0x5,%1,%3\;bcnd %#eq0,%d1,%2\", operands);
output_label (label_num);
return \"\";
}"
[(set_attr "type" "branch")])
[(set_attr "type" "weird")
(set_attr "length" "3")])
;; Recognize bb0 and bb1 instructions. These use two unusual template
;; patterns, %Lx and %Px. %Lx outputs a 1 if operand `x' is a LABEL_REF
......@@ -1372,7 +1373,7 @@
(match_operand 2 "pc_or_label_ref" "")
(match_operand 3 "pc_or_label_ref" "")))]
""
"bb1%. %R3%C0,%1,%P2%P3"
"bb%L2 %C0,%1,%P2%P3"
[(set_attr "type" "branch")])
(define_insn ""
......@@ -1385,7 +1386,7 @@
(match_operand 2 "pc_or_label_ref" "")
(match_operand 3 "pc_or_label_ref" "")))]
""
"bb0%. %R3%C0,%1,%P2%P3"
"bb%L3 %C0,%1,%P2%P3"
[(set_attr "type" "branch")])
(define_insn "locate1"
......@@ -1439,15 +1440,15 @@
|| operands[1] == const0_rtx)"
"@
or %0,%#r0,%1
%V1ld %0,%1
%v0st %r1,%0
%V1ld\\t %0,%1
%v0st\\t %r1,%0
subu %0,%#r0,%n1
set %0,%#r0,%s1
mov.s %0,%1
mov.s %0,%1
mov %0,%1
%V1ld %0,%1
%v0st %1,%0"
%V1ld\\t %0,%1
%v0st\\t %1,%0"
[(set_attr "type" "arith,load,store,arith,bit,mov,mov,mov,load,store")])
(define_insn ""
......@@ -1496,8 +1497,8 @@
|| operands[1] == const0_rtx)"
"@
or %0,%#r0,%h1
%V1ld.hu %0,%1
%v0st.h %r1,%0
%V1ld.hu\\t %0,%1
%v0st.h\\t %r1,%0
subu %0,%#r0,%H1"
[(set_attr "type" "arith,load,store,arith")])
......@@ -1528,8 +1529,8 @@
|| operands[1] == const0_rtx)"
"@
or %0,%#r0,%q1
%V1ld.bu %0,%1
%v0st.b %r1,%0
%V1ld.bu\\t %0,%1
%v0st.b\\t %r1,%0
subu %r0,%#r0,%Q1"
[(set_attr "type" "arith,load,store,arith")])
......@@ -1567,13 +1568,13 @@
""
"@
or %0,%#r0,%1\;or %d0,%#r0,%d1
%V1ld.d %0,%1
%v0st.d %1,%0
%V1ld.d\\t %0,%1
%v0st.d\\t %1,%0
mov.d %0,%1
mov.d %0,%1
mov %0,%1
%V1ld.d %0,%1
%v0st.d %1,%0"
%V1ld.d\\t %0,%1
%v0st.d\\t %1,%0"
[(set_attr "type" "marith,loadd,store,mov,mov,mov,loadd,store")])
(define_insn ""
......@@ -1621,7 +1622,7 @@
; return \"or %0,%#r0,0\;or %d0,%#r0,0\";
; case 1:
; operands[1] = adj_offsettable_operand (operands[0], 4);
; return \"%v0st %#r0,%0\;st %#r0,%1\";
; return \"%v0st\\t %#r0,%0\;st %#r0,%1\";
; }
;}")
......@@ -1640,13 +1641,13 @@
""
"@
or %0,%#r0,%1\;or %d0,%#r0,%d1
%V1ld.d %0,%1
%v0st.d %1,%0
%V1ld.d\\t %0,%1
%v0st.d\\t %1,%0
mov.d %0,%1
mov.d %0,%1
mov %0,%1
%V1ld.d %0,%1
%v0st.d %1,%0"
%V1ld.d\\t %0,%1
%v0st.d\\t %1,%0"
[(set_attr "type" "marith,loadd,store,mov,mov,mov,loadd,store")])
(define_insn ""
......@@ -1692,13 +1693,13 @@
""
"@
or %0,%#r0,%1
%V1ld %0,%1
%v0st %r1,%0
%V1ld\\t %0,%1
%v0st\\t %r1,%0
mov.s %0,%1
mov.s %0,%1
mov %0,%1
%V1ld %0,%1
%v0st %r1,%0"
%V1ld\\t %0,%1
%v0st\\t %r1,%0"
[(set_attr "type" "arith,load,store,mov,mov,mov,load,store")])
(define_insn ""
......@@ -1733,6 +1734,62 @@
DONE;
}")
(define_insn ""
[(set (match_operand:QI 0 "register_operand" "=r")
(match_operand:BLK 1 "memory_operand" "m"))]
""
"%V1ld.bu\\t %0,%1"
[(set_attr "type" "load")])
(define_insn ""
[(set (match_operand:HI 0 "register_operand" "=r")
(match_operand:BLK 1 "memory_operand" "m"))]
""
"%V1ld.hu\\t %0,%1"
[(set_attr "type" "load")])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r")
(match_operand:BLK 1 "memory_operand" "m"))]
""
"%V1ld\\t %0,%1"
[(set_attr "type" "load")])
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=r")
(match_operand:BLK 1 "memory_operand" "m"))]
""
"%V1ld.d\\t %0,%1"
[(set_attr "type" "loadd")])
(define_insn ""
[(set (match_operand:BLK 0 "memory_operand" "=m")
(match_operand:QI 1 "register_operand" "r"))]
""
"%v0st.b\\t %1,%0"
[(set_attr "type" "store")])
(define_insn ""
[(set (match_operand:BLK 0 "memory_operand" "=m")
(match_operand:HI 1 "register_operand" "r"))]
""
"%v0st.h\\t %1,%0"
[(set_attr "type" "store")])
(define_insn ""
[(set (match_operand:BLK 0 "memory_operand" "=m")
(match_operand:SI 1 "register_operand" "r"))]
""
"%v0st\\t %1,%0"
[(set_attr "type" "store")])
(define_insn ""
[(set (match_operand:BLK 0 "memory_operand" "=m")
(match_operand:DI 1 "register_operand" "r"))]
""
"%v0st.d\\t %1,%0"
[(set_attr "type" "store")])
;; Call a non-looping block move library function (e.g. __movstrSI96x64).
;; operand 0 is the function name
;; operand 1 is the destination pointer
......@@ -1766,7 +1823,7 @@
[(set (reg:SI 3) (minus:SI (match_operand:SI 2 "register_operand" "")
(match_operand:SI 3 "immediate_operand" "")))
(set (match_operand:SI 5 "register_operand" "")
(match_operand:SI 4 "memory_operand" ""))
(match_operand 4 "memory_operand" ""))
(set (reg:SI 2) (minus:SI (match_operand:SI 1 "register_operand" "")
(match_dup 3)))
(set (reg:SI 6) (match_operand:SI 6 "immediate_operand" ""))
......@@ -1802,7 +1859,7 @@
"@
mask %0,%1,0xffff
or %0,%#r0,%h1
%V1ld.hu %0,%1"
%V1ld.hu\\t %0,%1"
[(set_attr "type" "arith,arith,load")])
(define_expand "zero_extendqihi2"
......@@ -1824,7 +1881,7 @@
"@
mask %0,%1,0xff
or %0,%#r0,%q1
%V1ld.bu %0,%1"
%V1ld.bu\\t %0,%1"
[(set_attr "type" "arith,arith,load")])
(define_expand "zero_extendqisi2"
......@@ -1851,7 +1908,7 @@
"@
mask %0,%1,0xff
or %0,%#r0,%q1
%V1ld.bu %0,%1"
%V1ld.bu\\t %0,%1"
[(set_attr "type" "arith,arith,load")])
;;- sign extension instructions
......@@ -1885,7 +1942,7 @@
ext %0,%1,16<0>
or %0,%#r0,%h1
subu %0,%#r0,%H1
%V1ld.h %0,%1"
%V1ld.h\\t %0,%1"
[(set_attr "type" "bit,arith,arith,load")])
(define_expand "extendqihi2"
......@@ -1908,7 +1965,7 @@
ext %0,%1,8<0>
or %0,%#r0,%q1
subu %0,%#r0,%Q1
%V1ld.b %0,%1"
%V1ld.b\\t %0,%1"
[(set_attr "type" "bit,arith,arith,load")])
(define_expand "extendqisi2"
......@@ -1931,7 +1988,7 @@
ext %0,%1,8<0>
or %0,%#r0,%q1
subu %0,%#r0,%Q1
%V1ld.b %0,%1"
%V1ld.b\\t %0,%1"
[(set_attr "type" "bit,arith,arith,load")])
;; Conversions between float and double.
......@@ -2966,7 +3023,7 @@
(ashiftrt:SI (match_operand:SI 1 "memory_operand" "m")
(const_int 24)))]
"! SCALED_ADDRESS_P (XEXP (operands[1], 0))"
"%V1ld.b %0,%1"
"%V1ld.b\\t %0,%1"
[(set_attr "type" "load")])
(define_insn ""
......@@ -2974,7 +3031,7 @@
(lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
(const_int 24)))]
"! SCALED_ADDRESS_P (XEXP (operands[1], 0))"
"%V1ld.bu %0,%1"
"%V1ld.bu\\t %0,%1"
[(set_attr "type" "load")])
(define_insn ""
......@@ -2982,7 +3039,7 @@
(ashiftrt:SI (match_operand:SI 1 "memory_operand" "m")
(const_int 16)))]
"! SCALED_ADDRESS_P (XEXP (operands[1], 0))"
"%V1ld.h %0,%1"
"%V1ld.h\\t %0,%1"
[(set_attr "type" "load")])
(define_insn ""
......@@ -2990,7 +3047,7 @@
(lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
(const_int 16)))]
"! SCALED_ADDRESS_P (XEXP (operands[1], 0))"
"%V1ld.hu %0,%1"
"%V1ld.hu\\t %0,%1"
[(set_attr "type" "load")])
;;- arithmetic shift instructions.
......
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