Commit c3217088 by Peter Bergner

re PR testsuite/80546 (FAIL: gcc.target/powerpc/bool3-p[78].c scan-assembler-not)

	PR target/80546
	* config/rs6000/vsx.md (??r): New mode attribute.
	(*vsx_mov<mode>_64bit): Use it.
	(*vsx_mov<mode>_32bit): Likewise.

From-SVN: r258987
parent 815b2fc4
2018-03-30 Peter Bergner <bergner@vnet.ibm.com>
PR target/80546
* config/rs6000/vsx.md (??r): New mode attribute.
(*vsx_mov<mode>_64bit): Use it.
(*vsx_mov<mode>_32bit): Likewise.
2018-03-30 Martin Sebor <msebor@redhat.com>
PR tree-optimization/84818
......@@ -25,10 +32,10 @@
2018-03-29 Martin Liska <mliska@suse.cz>
PR lto/84995.
* doc/invoke.texi: Document how LTO works with debug info.
Describe auto-load support of binutils. Mention 'x86-64'
as valid option value of -march option.
PR lto/84995.
* doc/invoke.texi: Document how LTO works with debug info.
Describe auto-load support of binutils. Mention 'x86-64'
as valid option value of -march option.
2018-03-29 Jakub Jelinek <jakub@redhat.com>
......
......@@ -170,6 +170,19 @@
(TF "wp")
(KF "wq")])
;; A mode attribute to disparage use of GPR registers, except for scalar
;; integer modes.
(define_mode_attr ??r [(V16QI "??r")
(V8HI "??r")
(V4SI "??r")
(V4SF "??r")
(V2DI "??r")
(V2DF "??r")
(V1TI "??r")
(KF "??r")
(TF "??r")
(TI "r")])
;; Same size integer type for floating point data
(define_mode_attr VSi [(V4SF "v4si")
(V2DF "v2di")
......@@ -1200,7 +1213,7 @@
(define_insn "*vsx_mov<mode>_64bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, <VSa>, <VSa>, r, we, ?wQ,
?&r, ??r, ??Y, ??r, wo, v,
?&r, ??r, ??Y, <??r>, wo, v,
?<VSa>, *r, v, ??r, wZ, v")
(match_operand:VSX_M 1 "input_operand"
......@@ -1229,7 +1242,7 @@
;; LVX (VMX) STVX (VMX)
(define_insn "*vsx_mov<mode>_32bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, <VSa>, <VSa>, ??r, ??Y, ??r,
"=ZwO, <VSa>, <VSa>, ??r, ??Y, <??r>,
wo, v, ?<VSa>, *r, v, ??r,
wZ, v")
......
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