Commit c2ad275a by Jeffrey A Law Committed by Jeff Law

m68k.md (ashldi_const): Disable for !TARGET_5200.

       * m68k.md (ashldi_const): Disable for !TARGET_5200.  Fix indention.
        (ashldi3 expander): Similarly.  Update comments.
        (ashrdi_const, lshrdi_const): Fix indention.
        (ashrdi3, lshrdi3): FIx indention.  Update comments.

From-SVN: r24814
parent 23886015
Thu Jan 21 23:21:57 1999 Jeffrey A Law (law@cygnus.com)
* m68k.md (ashldi_const): Disable for !TARGET_5200. Fix indention.
(ashldi3 expander): Similarly. Update comments.
(ashrdi_const, lshrdi_const): Fix indention.
(ashrdi3, lshrdi3): FIx indention. Update comments.
Thu Jan 21 21:53:36 1999 Richard Henderson <rth@cygnus.com> Thu Jan 21 21:53:36 1999 Richard Henderson <rth@cygnus.com>
* emit-rtl.c (try_split): Don't try to split non-instructions. * emit-rtl.c (try_split): Don't try to split non-instructions.
......
;;- Machine description for GNU compiler, Motorola 68000 Version ;;- Machine description for GNU compiler, Motorola 68000 Version
;; Copyright (C) 1987, 88, 93-97, 1998 Free Software Foundation, Inc. ;; Copyright (C) 1987, 88, 93-98, 1999 Free Software Foundation, Inc.
;; This file is part of GNU CC. ;; This file is part of GNU CC.
...@@ -4563,9 +4563,10 @@ ...@@ -4563,9 +4563,10 @@
[(set (match_operand:DI 0 "general_operand" "=d") [(set (match_operand:DI 0 "general_operand" "=d")
(ashift:DI (match_operand:DI 1 "general_operand" "0") (ashift:DI (match_operand:DI 1 "general_operand" "0")
(match_operand 2 "const_int_operand" "n")))] (match_operand 2 "const_int_operand" "n")))]
"((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3) "(!TARGET_5200
|| INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
|| (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63))" || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
|| (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
"* "*
{ {
operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
...@@ -4594,13 +4595,15 @@ ...@@ -4594,13 +4595,15 @@
[(set (match_operand:DI 0 "general_operand" "") [(set (match_operand:DI 0 "general_operand" "")
(ashift:DI (match_operand:DI 1 "general_operand" "") (ashift:DI (match_operand:DI 1 "general_operand" "")
(match_operand 2 "const_int_operand" "")))] (match_operand 2 "const_int_operand" "")))]
"" "!TARGET_5200"
" "
{ {
/* ??? This is a named pattern like this is not allowed to FAIL based
on its operands. */
if (GET_CODE (operands[2]) != CONST_INT if (GET_CODE (operands[2]) != CONST_INT
|| ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3) || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
&& INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
&& (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63))) && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
FAIL; FAIL;
} ") } ")
...@@ -4763,11 +4766,11 @@ ...@@ -4763,11 +4766,11 @@
[(set (match_operand:DI 0 "general_operand" "=d") [(set (match_operand:DI 0 "general_operand" "=d")
(ashiftrt:DI (match_operand:DI 1 "general_operand" "0") (ashiftrt:DI (match_operand:DI 1 "general_operand" "0")
(match_operand 2 "const_int_operand" "n")))] (match_operand 2 "const_int_operand" "n")))]
"!TARGET_5200 "(!TARGET_5200
&& ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3) && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
|| INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
|| INTVAL (operands[2]) == 31 || INTVAL (operands[2]) == 31
|| (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63))" || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
"* "*
{ {
operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
...@@ -4806,10 +4809,12 @@ ...@@ -4806,10 +4809,12 @@
"!TARGET_5200" "!TARGET_5200"
" "
{ {
/* ??? This is a named pattern like this is not allowed to FAIL based
on its operands. */
if (GET_CODE (operands[2]) != CONST_INT if (GET_CODE (operands[2]) != CONST_INT
|| ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3) || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
&& INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
&& (INTVAL (operands[2]) < 31 || INTVAL (operands[2]) > 63))) && (INTVAL (operands[2]) < 31 || INTVAL (operands[2]) > 63)))
FAIL; FAIL;
} ") } ")
...@@ -4934,10 +4939,10 @@ ...@@ -4934,10 +4939,10 @@
[(set (match_operand:DI 0 "general_operand" "=d") [(set (match_operand:DI 0 "general_operand" "=d")
(lshiftrt:DI (match_operand:DI 1 "general_operand" "0") (lshiftrt:DI (match_operand:DI 1 "general_operand" "0")
(match_operand 2 "const_int_operand" "n")))] (match_operand 2 "const_int_operand" "n")))]
"!TARGET_5200 "(!TARGET_5200
&& ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3) && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
|| INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
|| (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63))" || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
"* "*
{ {
operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
...@@ -4972,10 +4977,12 @@ ...@@ -4972,10 +4977,12 @@
"!TARGET_5200" "!TARGET_5200"
" "
{ {
/* ??? This is a named pattern like this is not allowed to FAIL based
on its operands. */
if (GET_CODE (operands[2]) != CONST_INT if (GET_CODE (operands[2]) != CONST_INT
|| ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3) || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
&& INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
&& (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63))) && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
FAIL; FAIL;
} ") } ")
......
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