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riscv-gcc-1
Commit c29e2982 by Bernd Schmidt Committed by Bernd Schmidt
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thumb2.md (thumb2_notsi_shiftsi, [...]): Delete. 

	* config/arm/thumb2.md (thumb2_notsi_shiftsi,
	thumbsi_notsi_shiftsi_compare0, thumb2_not_shiftsi_compare0_scratch,
	thumb2_cmpsi_shiftsi, thumb2_cmpsi_shiftsi_swp, thumb2_arith_shiftsi,
	thumb2_arith_shiftsi splitter, thumb2_arith_shiftsi_compare0,
	thumb2_arith_shiftsi_compare0_scratch, thumb2_sub_shiftsi,
	thumb2_sub_shiftsi_compare0, thumb2_sub_shiftsi_compare0_scratch,
	thumb2_iorsi3): Delete.
	(orsi_notsi_si): No longer a named pattern.
	(orsi_not_shiftsi_si): Renamed from thumb_orsi_not_shiftsi_si.
	* config/arm/predicates.md (shift_amount_operand): New.
	(mult_operator): New.
	* config/arm/arm.md (attr arch, attr arch_enabled, attr insn_enabled,
	attr enabled): New.
	(iorsi3_insn): Renamed from arm_iorsi3.  Handle a new alternative if
	arch matches t2.
	(not_shiftsi): Renamed from arm_notsi_shiftsi.  Handle Thumb2 variant.
	(not_shiftsi_compare0): Likewise, renamed from
	arm_notsi_shiftsi_compare0.
	(not_shiftsi_compare0_scratch): Likweise, renamed from
	arm_notsi_shiftsi_compare0_scratch.
	(cmpsi_shiftsi): Likewise, renamed from arm_cmpsi_shiftsi.
	(cmpsi_shiftsi_swp): Likewise, renamed from arm_cmpsi_shiftsi_swp.
	(arith_shiftsi): Handle Thumb2 variant.  Set insn_enabled attribute
	so that the register alternative is disabled when the shift_operator
	is MULT.  Use "M" as the constraint for constants.
	(arith_shiftsi splitter): Enable for TARGET_32BIT.
	(arith_shiftsi_compare0): Handle Thumb2 variant.  Use "M" as the
	constraint for constants.
	(arith_shiftsi_compare0_scratch): Likewise.
	(sub_shiftsi, sub_shiftsi_compare0, sub_shiftsi_compare0_scratch):
	Handle Thumb2 alternative.

From-SVN: r163281
parent c878765b
Showing with 45 additions and 208 deletions
gcc/ChangeLog
2010-08-16 Bernd Schmidt <bernds@codesourcery.com>
* config/arm/thumb2.md (thumb2_notsi_shiftsi,
thumbsi_notsi_shiftsi_compare0, thumb2_not_shiftsi_compare0_scratch,
thumb2_cmpsi_shiftsi, thumb2_cmpsi_shiftsi_swp, thumb2_arith_shiftsi,
thumb2_arith_shiftsi splitter, thumb2_arith_shiftsi_compare0,
thumb2_arith_shiftsi_compare0_scratch, thumb2_sub_shiftsi,
thumb2_sub_shiftsi_compare0, thumb2_sub_shiftsi_compare0_scratch,
thumb2_iorsi3): Delete.
(orsi_notsi_si): No longer a named pattern.
(orsi_not_shiftsi_si): Renamed from thumb_orsi_not_shiftsi_si.
* config/arm/predicates.md (shift_amount_operand): New.
(mult_operator): New.
* config/arm/arm.md (attr arch, attr arch_enabled, attr insn_enabled,
attr enabled): New.
(iorsi3_insn): Renamed from arm_iorsi3. Handle a new alternative if
arch matches t2.
(not_shiftsi): Renamed from arm_notsi_shiftsi. Handle Thumb2 variant.
(not_shiftsi_compare0): Likewise, renamed from
arm_notsi_shiftsi_compare0.
(not_shiftsi_compare0_scratch): Likweise, renamed from
arm_notsi_shiftsi_compare0_scratch.
(cmpsi_shiftsi): Likewise, renamed from arm_cmpsi_shiftsi.
(cmpsi_shiftsi_swp): Likewise, renamed from arm_cmpsi_shiftsi_swp.
(arith_shiftsi): Handle Thumb2 variant. Set insn_enabled attribute
so that the register alternative is disabled when the shift_operator
is MULT. Use "M" as the constraint for constants.
(arith_shiftsi splitter): Enable for TARGET_32BIT.
(arith_shiftsi_compare0): Handle Thumb2 variant. Use "M" as the
constraint for constants.
(arith_shiftsi_compare0_scratch): Likewise.
(sub_shiftsi, sub_shiftsi_compare0, sub_shiftsi_compare0_scratch):
Handle Thumb2 alternative.
2010-08-16 Joseph Myers <joseph@codesourcery.com>
* doc/options.texi (NoDriverArg): Document.
......
gcc/config/arm/predicates.md
......@@ -128,6 +128,11 @@
(ior (match_operand 0 "arm_rhs_operand")
(match_operand 0 "memory_operand")))
(define_predicate "shift_amount_operand"
(ior (and (match_test "TARGET_ARM")
(match_operand 0 "s_register_operand"))
(match_operand 0 "const_int_operand")))
(define_predicate "arm_add_operand"
(ior (match_operand 0 "arm_rhs_operand")
(match_operand 0 "arm_neg_immediate_operand")))
......@@ -221,6 +226,10 @@
(match_code "ashift,ashiftrt,lshiftrt,rotatert"))
(match_test "mode == GET_MODE (op)")))
;; True for MULT, to identify which variant of shift_operator is in use.
(define_special_predicate "mult_operator"
(match_code "mult"))
;; True for operators that have 16-bit thumb variants. */
(define_special_predicate "thumb_16bit_operator"
(match_code "plus,minus,and,ior,xor"))
......
gcc/config/arm/thumb2.md
......@@ -120,47 +120,6 @@
(set_attr "length" "10,10,14")]
)
(define_insn "*thumb2_notsi_shiftsi"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(not:SI (match_operator:SI 3 "shift_operator"
[(match_operand:SI 1 "s_register_operand" "r")
(match_operand:SI 2 "const_int_operand" "M")])))]
"TARGET_THUMB2"
"mvn%?\\t%0, %1%S3"
[(set_attr "predicable" "yes")
(set_attr "shift" "1")
(set_attr "type" "alu_shift")]
)
(define_insn "*thumb2_notsi_shiftsi_compare0"
[(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV (not:SI (match_operator:SI 3 "shift_operator"
[(match_operand:SI 1 "s_register_operand" "r")
(match_operand:SI 2 "const_int_operand" "M")]))
(const_int 0)))
(set (match_operand:SI 0 "s_register_operand" "=r")
(not:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)])))]
"TARGET_THUMB2"
"mvn%.\\t%0, %1%S3"
[(set_attr "conds" "set")
(set_attr "shift" "1")
(set_attr "type" "alu_shift")]
)
(define_insn "*thumb2_not_shiftsi_compare0_scratch"
[(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV (not:SI (match_operator:SI 3 "shift_operator"
[(match_operand:SI 1 "s_register_operand" "r")
(match_operand:SI 2 "const_int_operand" "M")]))
(const_int 0)))
(clobber (match_scratch:SI 0 "=r"))]
"TARGET_THUMB2"
"mvn%.\\t%0, %1%S3"
[(set_attr "conds" "set")
(set_attr "shift" "1")
(set_attr "type" "alu_shift")]
)
;; Thumb-2 does not have rsc, so use a clever trick with shifter operands.
(define_insn "*thumb2_negdi2"
[(set (match_operand:DI 0 "s_register_operand" "=&r,r")
......@@ -260,32 +219,6 @@
(set_attr "neg_pool_range" "*,*,*,250")]
)
(define_insn "*thumb2_cmpsi_shiftsi"
[(set (reg:CC CC_REGNUM)
(compare:CC (match_operand:SI 0 "s_register_operand" "r")
(match_operator:SI 3 "shift_operator"
[(match_operand:SI 1 "s_register_operand" "r")
(match_operand:SI 2 "const_int_operand" "M")])))]
"TARGET_THUMB2"
"cmp%?\\t%0, %1%S3"
[(set_attr "conds" "set")
(set_attr "shift" "1")
(set_attr "type" "alu_shift")]
)
(define_insn "*thumb2_cmpsi_shiftsi_swp"
[(set (reg:CC_SWP CC_REGNUM)
(compare:CC_SWP (match_operator:SI 3 "shift_operator"
[(match_operand:SI 1 "s_register_operand" "r")
(match_operand:SI 2 "const_int_operand" "M")])
(match_operand:SI 0 "s_register_operand" "r")))]
"TARGET_THUMB2"
"cmp%?\\t%0, %1%S3"
[(set_attr "conds" "set")
(set_attr "shift" "1")
(set_attr "type" "alu_shift")]
)
(define_insn "*thumb2_cmpsi_neg_shiftsi"
[(set (reg:CC CC_REGNUM)
(compare:CC (match_operand:SI 0 "s_register_operand" "r")
......@@ -396,122 +329,6 @@
;; addresses will have the thumb bit set correctly.
;; Patterns to allow combination of arithmetic, cond code and shifts
(define_insn "*thumb2_arith_shiftsi"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(match_operator:SI 1 "shiftable_operator"
[(match_operator:SI 3 "shift_operator"
[(match_operand:SI 4 "s_register_operand" "r")
(match_operand:SI 5 "const_int_operand" "M")])
(match_operand:SI 2 "s_register_operand" "rk")]))]
"TARGET_THUMB2"
"%i1%?\\t%0, %2, %4%S3"
[(set_attr "predicable" "yes")
(set_attr "shift" "4")
(set_attr "type" "alu_shift")]
)
;; ??? What does this splitter do? Copied from the ARM version
(define_split
[(set (match_operand:SI 0 "s_register_operand" "")
(match_operator:SI 1 "shiftable_operator"
[(match_operator:SI 2 "shiftable_operator"
[(match_operator:SI 3 "shift_operator"
[(match_operand:SI 4 "s_register_operand" "")
(match_operand:SI 5 "const_int_operand" "")])
(match_operand:SI 6 "s_register_operand" "")])
(match_operand:SI 7 "arm_rhs_operand" "")]))
(clobber (match_operand:SI 8 "s_register_operand" ""))]
"TARGET_32BIT"
[(set (match_dup 8)
(match_op_dup 2 [(match_op_dup 3 [(match_dup 4) (match_dup 5)])
(match_dup 6)]))
(set (match_dup 0)
(match_op_dup 1 [(match_dup 8) (match_dup 7)]))]
"")
(define_insn "*thumb2_arith_shiftsi_compare0"
[(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV (match_operator:SI 1 "shiftable_operator"
[(match_operator:SI 3 "shift_operator"
[(match_operand:SI 4 "s_register_operand" "r")
(match_operand:SI 5 "const_int_operand" "M")])
(match_operand:SI 2 "s_register_operand" "r")])
(const_int 0)))
(set (match_operand:SI 0 "s_register_operand" "=r")
(match_op_dup 1 [(match_op_dup 3 [(match_dup 4) (match_dup 5)])
(match_dup 2)]))]
"TARGET_32BIT"
"%i1%.\\t%0, %2, %4%S3"
[(set_attr "conds" "set")
(set_attr "shift" "4")
(set_attr "type" "alu_shift")]
)
(define_insn "*thumb2_arith_shiftsi_compare0_scratch"
[(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV (match_operator:SI 1 "shiftable_operator"
[(match_operator:SI 3 "shift_operator"
[(match_operand:SI 4 "s_register_operand" "r")
(match_operand:SI 5 "const_int_operand" "M")])
(match_operand:SI 2 "s_register_operand" "r")])
(const_int 0)))
(clobber (match_scratch:SI 0 "=r"))]
"TARGET_THUMB2"
"%i1%.\\t%0, %2, %4%S3"
[(set_attr "conds" "set")
(set_attr "shift" "4")
(set_attr "type" "alu_shift")]
)
(define_insn "*thumb2_sub_shiftsi"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(minus:SI (match_operand:SI 1 "s_register_operand" "r")
(match_operator:SI 2 "shift_operator"
[(match_operand:SI 3 "s_register_operand" "r")
(match_operand:SI 4 "const_int_operand" "M")])))]
"TARGET_THUMB2"
"sub%?\\t%0, %1, %3%S2"
[(set_attr "predicable" "yes")
(set_attr "shift" "3")
(set_attr "type" "alu_shift")]
)
(define_insn "*thumb2_sub_shiftsi_compare0"
[(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV
(minus:SI (match_operand:SI 1 "s_register_operand" "r")
(match_operator:SI 2 "shift_operator"
[(match_operand:SI 3 "s_register_operand" "r")
(match_operand:SI 4 "const_int_operand" "M")]))
(const_int 0)))
(set (match_operand:SI 0 "s_register_operand" "=r")
(minus:SI (match_dup 1) (match_op_dup 2 [(match_dup 3)
(match_dup 4)])))]
"TARGET_THUMB2"
"sub%.\\t%0, %1, %3%S2"
[(set_attr "conds" "set")
(set_attr "shift" "3")
(set_attr "type" "alu_shift")]
)
(define_insn "*thumb2_sub_shiftsi_compare0_scratch"
[(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV
(minus:SI (match_operand:SI 1 "s_register_operand" "r")
(match_operator:SI 2 "shift_operator"
[(match_operand:SI 3 "s_register_operand" "r")
(match_operand:SI 4 "const_int_operand" "M")]))
(const_int 0)))
(clobber (match_scratch:SI 0 "=r"))]
"TARGET_THUMB2"
"sub%.\\t%0, %1, %3%S2"
[(set_attr "conds" "set")
(set_attr "shift" "3")
(set_attr "type" "alu_shift")]
)
(define_insn "*thumb2_and_scc"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(and:SI (match_operator:SI 1 "arm_comparison_operator"
......@@ -1365,7 +1182,7 @@
(set_attr "length" "2")]
)
(define_insn "orsi_notsi_si"
(define_insn "*orsi_notsi_si"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(ior:SI (not:SI (match_operand:SI 2 "s_register_operand" "r"))
(match_operand:SI 1 "s_register_operand" "r")))]
......@@ -1374,7 +1191,7 @@
[(set_attr "predicable" "yes")]
)
(define_insn "*thumb_orsi_not_shiftsi_si"
(define_insn "*orsi_not_shiftsi_si"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(ior:SI (not:SI (match_operator:SI 4 "shift_operator"
[(match_operand:SI 2 "s_register_operand" "r")
......@@ -1387,29 +1204,6 @@
(set_attr "type" "alu_shift")]
)
(define_insn_and_split "*thumb2_iorsi3"
[(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
(ior:SI (match_operand:SI 1 "s_register_operand" "r,r,r")
(match_operand:SI 2 "reg_or_int_operand" "rI,K,?n")))]
"TARGET_THUMB2"
"@
orr%?\\t%0, %1, %2
orn%?\\t%0, %1, #%B2
#"
"TARGET_THUMB2
&& GET_CODE (operands[2]) == CONST_INT
&& !(const_ok_for_arm (INTVAL (operands[2]))
|| const_ok_for_arm (~INTVAL (operands[2])))"
[(clobber (const_int 0))]
"
arm_split_constant (IOR, SImode, curr_insn,
INTVAL (operands[2]), operands[0], operands[1], 0);
DONE;
"
[(set_attr "length" "4,4,16")
(set_attr "predicable" "yes")]
)
(define_peephole2
[(set (match_operand:CC_NOOV 0 "cc_register" "")
(compare:CC_NOOV (zero_extract:SI
......
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