Add support for the FCCMP insn types

2016-01-21  Evandro Menezes  <e.menezes@samsung.com>

gcc/
	* config/aarch64/aarch64.md (fccmp): Change insn type.
	(fccmpe): Likewise.
	* config/aarch64/thunderx.md (thunderx_fcmp): Add "fccmp{s,d}" types.
	* config/arm/cortex-a53.md (cortex_a53_fpalu): Likewise.
	* config/arm/cortex-a57.md (cortex_a57_fp_cmp): Likewise.
	* config/arm/xgene1.md (xgene1_fcmp): Likewise.
	* config/arm/exynos-m1.md (exynos_m1_fp_ccmp): New insn reservation.
	* config/arm/types.md (fccmps): Add new insn type.
	(fccmpd): Likewise.

From-SVN: r233432

gcc/ChangeLog

+2016-02-15  Evandro Menezes  <e.menezes@samsung.com>
+    
+	Add support for the FCCMP insn types
+
+	* config/aarch64/aarch64.md (fccmp): Change insn type.
+	(fccmpe): Likewise.
+	* config/aarch64/thunderx.md (thunderx_fcmp): Add "fccmp{s,d}" types.
+	* config/arm/cortex-a53.md (cortex_a53_fpalu): Likewise.
+	* config/arm/cortex-a57.md (cortex_a57_fp_cmp): Likewise.
+	* config/arm/xgene1.md (xgene1_fcmp): Likewise.
+	* config/arm/exynos-m1.md (exynos_m1_fp_ccmp): New insn reservation.
+	* config/arm/types.md (fccmps): Add new insn type.
+	(fccmpd): Likewise.
+
 2016-02-15  Bernd Edlinger  <bernd.edlinger@hotmail.de>
 
 	* alias.c (get_alias_set): Fix a typo in comment.

gcc/config/aarch64/aarch64.md

@@ -302,7 +302,7 @@
 	  (unspec:CCFP [(match_operand 5 "immediate_operand")] UNSPEC_NZCV)))]
   "TARGET_FLOAT"
   "fccmp\\t%<s>2, %<s>3, %k5, %m4"
-  [(set_attr "type" "fcmp<s>")]
+  [(set_attr "type" "fccmp<s>")]
 )
 
 (define_insn "fccmpe<mode>"
@@ -317,7 +317,7 @@
 	  (unspec:CCFPE [(match_operand 5 "immediate_operand")] UNSPEC_NZCV)))]
   "TARGET_FLOAT"
   "fccmpe\\t%<s>2, %<s>3, %k5, %m4"
-  [(set_attr "type" "fcmp<s>")]
+  [(set_attr "type" "fccmp<s>")]
 )
 
 ;; Expansion of signed mod by a power of 2 using CSNEG.

gcc/config/aarch64/thunderx.md

@@ -156,7 +156,7 @@
 
 (define_insn_reservation "thunderx_fcmp" 3
   (and (eq_attr "tune" "thunderx")
-       (eq_attr "type" "fcmps,fcmpd"))
+       (eq_attr "type" "fcmps,fcmpd,fccmps,fccmpd"))
   "thunderx_pipe1")
 
 (define_insn_reservation "thunderx_fmul" 6

gcc/config/arm/cortex-a53.md

@@ -508,8 +508,8 @@
 (define_insn_reservation "cortex_a53_fpalu" 5
   (and (eq_attr "tune" "cortexa53")
 	(eq_attr "type" "ffariths, fadds, ffarithd, faddd, fmov,
-			f_cvt, fcmps, fcmpd, fcsel, f_rints, f_rintd,
-			f_minmaxs, f_minmaxd"))
+			f_cvt, fcmps, fcmpd, fccmps, fccmpd, fcsel,
+			f_rints, f_rintd, f_minmaxs, f_minmaxd"))
   "cortex_a53_slot_any,cortex_a53_fp_alu")
 
 (define_insn_reservation "cortex_a53_fconst" 3

gcc/config/arm/cortex-a57.md

@@ -716,7 +716,7 @@
 
 (define_insn_reservation "cortex_a57_fp_cmp" 7
   (and (eq_attr "tune" "cortexa57")
-       (eq_attr "type" "fcmps,fcmpd"))
+       (eq_attr "type" "fcmps,fcmpd,fccmps,fccmpd"))
   "ca57_cx2")
 
 (define_insn_reservation "cortex_a57_fp_arith" 4

gcc/config/arm/exynos-m1.md

@@ -823,6 +823,11 @@
        (eq_attr "type" "fcmps, fcmpd"))
   "em1_nmisc")
 
+(define_insn_reservation "exynos_m1_fp_ccmp" 7
+  (and (eq_attr "tune" "exynosm1")
+       (eq_attr "type" "fccmps, fccmpd"))
+  "(em1_st, em1_nmisc)")
+
 (define_insn_reservation "exynos_m1_fp_sel" 4
   (and (eq_attr "tune" "exynosm1")
        (eq_attr "type" "fcsel"))

gcc/config/arm/types.md

@@ -70,6 +70,7 @@
 ; f_rint[d,s]        double/single floating point rount to integral.
 ; f_store[d,s]       double/single store to memory.  Used for VFP unit.
 ; fadd[d,s]          double/single floating-point scalar addition.
+; fccmp[d,s]         From ARMv8-A: floating-point conditional compare.
 ; fcmp[d,s]          double/single floating-point compare.
 ; fconst[d,s]        double/single load immediate.
 ; fcsel              From ARMv8-A: Floating-point conditional select.
@@ -582,6 +583,8 @@
   f_stores,\
   faddd,\
   fadds,\
+  fccmpd,\
+  fccmps,\
   fcmpd,\
   fcmps,\
   fconstd,\

gcc/config/arm/xgene1.md

@@ -154,7 +154,7 @@
 
 (define_insn_reservation "xgene1_fcmp" 10
   (and (eq_attr "tune" "xgene1")
-       (eq_attr "type" "fcmpd,fcmps"))
+       (eq_attr "type" "fcmpd,fcmps,fccmpd,fccmps"))
   "xgene1_decode1op,xgene1_fsu+xgene1_fcmp*3")
 
 (define_insn_reservation "xgene1_fcsel" 3