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riscv-gcc-1
Commit c2540bbb by Daniel Jacobowitz Committed by Daniel Jacobowitz
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* config/arm/arm.md (insv): Use gen_int_mode in more places. 

From-SVN: r104997
parent f3940b0e
Showing with 8 additions and 3 deletions
gcc/ChangeLog
2005-10-05 Daniel Jacobowitz <dan@codesourcery.com>
* config/arm/arm.md (insv): Use gen_int_mode in more places.
2005-10-05 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/18587
......
gcc/config/arm/arm.md
......@@ -1901,7 +1901,8 @@
HOST_WIDE_INT op3_value = mask & INTVAL (operands[3]);
HOST_WIDE_INT mask2 = ((mask & ~op3_value) << start_bit);
emit_insn (gen_andsi3 (op1, operands[0], GEN_INT (~mask2)));
emit_insn (gen_andsi3 (op1, operands[0],
gen_int_mode (~mask2, SImode)));
emit_insn (gen_iorsi3 (subtarget, op1,
gen_int_mode (op3_value << start_bit, SImode)));
}
......@@ -1939,7 +1940,7 @@
}
else
{
rtx op0 = GEN_INT (mask);
rtx op0 = gen_int_mode (mask, SImode);
rtx op1 = gen_reg_rtx (SImode);
rtx op2 = gen_reg_rtx (SImode);
......@@ -1958,7 +1959,7 @@
&& (const_ok_for_arm (mask << start_bit)
|| const_ok_for_arm (~(mask << start_bit))))
{
op0 = GEN_INT (~(mask << start_bit));
op0 = gen_int_mode (~(mask << start_bit), SImode);
emit_insn (gen_andsi3 (op2, operands[0], op0));
}
else
......
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