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riscv-gcc-1
Commit c1c691dd by Richard Stallman
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entered into RCS 

From-SVN: r892
parent 7c6d68c8
Showing with 112 additions and 62 deletions
gcc/config/we32k/we32k.md
...@@ -739,25 +739,42 @@ ...@@ -739,25 +739,42 @@
"" ""
"mcomb %1, %0") "mcomb %1, %0")
;; test instruction
;; We don't want to allow a constant operand for test insns because
;; (set (cc0) (const_int foo)) has no mode information. Such insns will
;; be folded while optimizing anyway.
(define_insn "tstsi"
[(set (cc0) (match_operand:SI 0 "nonimmediate_operand" "mr"))]
""
"TSTW %0")
(define_insn "tsthi"
[(set (cc0) (match_operand:HI 0 "nonimmediate_operand" "mr"))]
""
"TSTH %0")
(define_insn "tstqi"
[(set (cc0) (match_operand:QI 0 "nonimmediate_operand" "mr"))]
""
"TSTB {sbyte}%0")
;; compare instruction ;; compare instruction
(define_insn "cmpsi" (define_insn "cmpsi"
[(set (cc0) (compare (match_operand:SI 0 "general_operand" "mri") [(set (cc0) (compare (match_operand:SI 0 "nonimmediate_operand" "mr")
(match_operand:SI 1 "general_operand" "mri")))] (match_operand:SI 1 "general_operand" "mri")))]
"" ""
"CMPW %1, %0") "CMPW %1, %0")
(define_insn "cmphi" (define_insn "cmphi"
[(set (cc0) (compare (match_operand:HI 0 "general_operand" "mri") [(set (cc0) (compare (match_operand:HI 0 "nonimmediate_operand" "mr")
(match_operand:HI 1 "general_operand" "mri")))] (match_operand:HI 1 "general_operand" "mri")))]
"" ""
"* "*
{ {
if (GET_CODE (operands[0]) == CONST_INT &&
((unsigned long)INTVAL (operands[0]) & 0x8000L))
operands[0] = gen_rtx(CONST_INT, SImode, INTVAL(operands[0]) | 0xffff0000L);
if (GET_CODE (operands[1]) == CONST_INT && if (GET_CODE (operands[1]) == CONST_INT &&
((unsigned long)INTVAL (operands[1]) & 0x8000L)) ((unsigned long)INTVAL (operands[1]) & 0x8000L))
operands[1] = gen_rtx(CONST_INT, SImode, INTVAL(operands[1]) | 0xffff0000L); operands[1] = gen_rtx(CONST_INT, SImode, INTVAL(operands[1]) | 0xffff0000L);
...@@ -768,16 +785,12 @@ ...@@ -768,16 +785,12 @@
}") }")
(define_insn "cmpqi" (define_insn "cmpqi"
[(set (cc0) (compare (match_operand:QI 0 "general_operand" "mri") [(set (cc0) (compare (match_operand:QI 0 "nonimmediate_operand" "mr")
(match_operand:QI 1 "general_operand" "mri")))] (match_operand:QI 1 "general_operand" "mri")))]
"" ""
"* "*
{ {
if (GET_CODE (operands[0]) == CONST_INT &&
((unsigned long)INTVAL (operands[0]) & 0x80L))
operands[0] = gen_rtx(CONST_INT, SImode, INTVAL(operands[0]) | 0xffffff00L);
if (GET_CODE (operands[1]) == CONST_INT && if (GET_CODE (operands[1]) == CONST_INT &&
((unsigned long)INTVAL (operands[1]) & 0x80L)) ((unsigned long)INTVAL (operands[1]) & 0x80L))
operands[1] = gen_rtx(CONST_INT, SImode, INTVAL(operands[1]) | 0xffffff00L); operands[1] = gen_rtx(CONST_INT, SImode, INTVAL(operands[1]) | 0xffffff00L);
...@@ -786,43 +799,6 @@ ...@@ -786,43 +799,6 @@
return \"\"; return \"\";
}") }")
;; test instruction
(define_insn "tstsi"
[(set (cc0) (match_operand:SI 0 "general_operand" "mri"))]
""
"TSTW %0")
(define_insn "tsthi"
[(set (cc0) (match_operand:HI 0 "general_operand" "mri"))]
""
"*
{
if (GET_CODE (operands[0]) == CONST_INT &&
((unsigned long)INTVAL (operands[0]) & 0x8000L))
operands[0] = gen_rtx(CONST_INT, SImode, INTVAL(operands[0]) | 0xffff0000L);
output_asm_insn(\"TSTH %0\",operands);
return \"\";
}")
(define_insn "tstqi"
[(set (cc0) (match_operand:QI 0 "general_operand" "mri"))]
""
"*
{
if (GET_CODE (operands[0]) == CONST_INT &&
((unsigned long)INTVAL (operands[0]) & 0x80L))
operands[0] = gen_rtx(CONST_INT, SImode, INTVAL(operands[0]) | 0xffffff00L);
output_asm_insn(\"TSTB {sbyte}%0\",operands);
return \"\";
}")
;; truncate instructions ;; truncate instructions
...@@ -928,21 +904,95 @@ ...@@ -928,21 +904,95 @@
;; bit field instructions ;; bit field instructions
;; (define_insn "extzv" (define_insn "extzv"
;; [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
;; (zero_extract:SI (match_operand:SI 1 "register_operand" "mr") (zero_extract:SI (match_operand:SI 1 "general_operand" "mri")
;; (match_operand:SI 2 "general_operand" "mri") (match_operand:SI 2 "immediate_operand" "i")
;; (match_operand:SI 3 "general_operand" "mri")))] (match_operand:SI 3 "general_operand" "mri")))]
;; "" ""
;; "EXTFW %2, %3, %1, %0") "*
{
;; (define_insn "insv" operands[2] = gen_rtx(CONST_INT, SImode, INTVAL(operands[2]) - 1);
;; [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+mr") output_asm_insn(\"EXTFW %2, %3, %1, %0\",operands);
;; (match_operand:SI 1 "general_operand" "mri")
;; (match_operand:SI 2 "general_operand" "mri")) return \"\";
;; (match_operand:SI 3 "general_operand" "mri"))] }")
;; ""
;; "INSFW %1, %2, %3, %0") (define_insn ""
[(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
(zero_extract:SI (match_operand:HI 1 "general_operand" "mri")
(match_operand:SI 2 "immediate_operand" "i")
(match_operand:SI 3 "general_operand" "mri")))]
""
"*
{
operands[2] = gen_rtx(CONST_INT, SImode, INTVAL(operands[2]) - 1);
output_asm_insn(\"EXTFH %2, %3, {uhalf}%1, {uword}%0\",operands);
return \"\";
}")
(define_insn ""
[(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
(zero_extract:SI (match_operand:QI 1 "general_operand" "mri")
(match_operand:SI 2 "immediate_operand" "i")
(match_operand:SI 3 "general_operand" "mri")))]
""
"*
{
operands[2] = gen_rtx(CONST_INT, SImode, INTVAL(operands[2]) - 1);
output_asm_insn(\"EXTFB %2, %3, {ubyte}%1, {uword}%0\",operands);
return \"\";
}")
(define_insn "insv"
[(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+mr")
(match_operand:SI 1 "immediate_operand" "i")
(match_operand:SI 2 "general_operand" "mri"))
(match_operand:SI 3 "general_operand" "mri"))]
""
"*
{
operands[1] = gen_rtx(CONST_INT, SImode, INTVAL(operands[1]) - 1);
output_asm_insn(\"INSFW %1, %2, %3, %0\",operands);
return \"\";
}")
(define_insn ""
[(set (zero_extract:SI (match_operand:HI 0 "nonimmediate_operand" "+mr")
(match_operand:SI 1 "immediate_operand" "i")
(match_operand:SI 2 "general_operand" "mri"))
(match_operand:SI 3 "general_operand" "mri"))]
""
"*
{
operands[1] = gen_rtx(CONST_INT, SImode, INTVAL(operands[1]) - 1);
output_asm_insn(\"INSFH %1, %2, {uword}%3, {uhalf}%0\",operands);
return \"\";
}")
(define_insn ""
[(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+mr")
(match_operand:SI 1 "immediate_operand" "i")
(match_operand:SI 2 "general_operand" "mri"))
(match_operand:SI 3 "general_operand" "mri"))]
""
"*
{
operands[1] = gen_rtx(CONST_INT, SImode, INTVAL(operands[1]) - 1);
output_asm_insn(\"INSFB %1, %2, {uword}%3, {ubyte}%0\",operands);
return \"\";
}")
;; conditional branch instructions ;; conditional branch instructions
......
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