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riscv-gcc-1
Commit c1b92d09 by J"orn Rennecke Committed by Joern Rennecke
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sh.c (langhooks.h): Include. 

	* sh.c (langhooks.h): Include.
	(sh_init_builtins, sh_media_init_builtins): New functions.
	(sh_expand_builtin, arith_reg_dest,and_operand): Likewise.
	(mextr_bit_offset, extend_reg_operand, zero_vec_operand): Likewise.
	(sh_rep_vec, sh_1el_vec, sh_const_vec): Likewise.
	(builtin_description): New struct tag.
	(signature_args, bdesc): New arrays.
	(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): Undef / define.
	(print_operand): Add 'N' modifier.
	* sh.h (VECTOR_MODE_SUPPORTED_P): Add SHmedia vector modes.
	(EXTRA_CONSTRAINT_U, EXTRA_CONSTRAINT_W): New macros.
	(EXTRA_CONSTRAINT): Add 'U' and 'W' cases.
	(CONST_COSTS): Add special case for SHmedia AND.
	(PREDICATE_CODES): Add and_operand, arith_reg_dest,
	extend_reg_operand, extend_reg_or_0_operand, mextr_bit_offset,
	sh_const_vec, sh_1el_vec, sh_rep_vec, zero_vec_operand.
	target_operand can also be const or unspec.
	* sh.md (UNSPEC_INIT_TRAMP, UNSPEC_FCOSA UNSPEC_FSRRA): New constants.
	(UNSPEC_FSINA, UNSPEC_NSB, UNSPEC_ALLOCO): Likewise.
	(attribute type): Add new types.
	(anddi3): Add splitter.
	(movdi_const_16bit+1): Add code to handle vector constants and
	bitmasks efficiently.
	(shori_media): Have generator function made.
	(movv8qi, movv8qi_i, movv8qi_i+1, movv8qi_i+2): New patterns.
	(movv8qi_i+3, movv2hi, movv2hi_i, movv4hi, movv4hi_i): Likewise.
	(movv2si, movv2si_i, absv2si2, absv4hi2, addv2si3, addv4hi3): Likewise.
	(ssaddv2si3, usaddv8qi3, ssaddv4hi3, negcmpeqv8qi): Likewise.
	(negcmpeqv2si, negcmpeqv4hi, negcmpgtuv8qi, negcmpgtv2si): Likewise.
	(negcmpgtv4hi, mcmv, mcnvs_lw, mcnvs_wb, mcnvs_wub): Likewise.
	(mextr_rl, mextr_lr, mextr1, mextr2, mextr3, mextr4, mextr5): Likewise.
	(mextr6, mextr7, mmacfx_wl, mmacfx_wl_i, mmacnfx_wl): Likewise.
	(mmacnfx_wl_i, mulv2si3, mulv4hi3, mmulfx_l, mmulfx_w): Likewise.
	(mmulfxrp_w, mmulhi_wl, mmullo_wl, mmul23_wl, mmul01_wl): Likewise.
	(mmulsum_wq, mmulsum_wq_i, mperm_w, mperm_w_little): LIkewise.
	(mperm_w_big, mperm_w0, msad_ubq, msad_ubq_i, mshalds_l): Likewise.
	(mshalds_w, ashrv2si3, ashrv4hi3, mshards_q, mshfhi_b): Likewise.
	(mshflo_b,  mshf4_b, mshf0_b, mshfhi_l, mshflo_l, mshf4_l): Likewsie.
	(mshf0_l, mshfhi_w, mshflo_w, mshf4_w, mshf0_w, mshfhi_l_di): Likewise.
	(mshfhi_l_di_rev, mshflo_l_di, mshflo_l_di_rev): Likewise.
	(mshflo_l_di_x, mshflo_l_di_x_rev, ashlv2si3, ashlv4hi3): Likewise.
	(lshrv2si3, lshrv4hi3, subv2si3, subv4hi3, sssubv2si3): Likewise.
	(ussubv8qi3, sssubv4hi3, fcosa_s, fsina_s, fipr, fsrra_s): Likewise.
	(ftrv): Likewise.

	(fpu_switch+1, fpu_switch+2): Remove constraint.

From-SVN: r55147
parent 7098b619
Showing with 84 additions and 5 deletions
gcc/ChangeLog
Mon Jul 1 19:55:17 2002 J"orn Rennecke <joern.rennecke@superh.com>
* sh.c (langhooks.h): Include.
(sh_init_builtins, sh_media_init_builtins): New functions.
(sh_expand_builtin, arith_reg_dest,and_operand): Likewise.
(mextr_bit_offset, extend_reg_operand, zero_vec_operand): Likewise.
(sh_rep_vec, sh_1el_vec, sh_const_vec): Likewise.
(builtin_description): New struct tag.
(signature_args, bdesc): New arrays.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): Undef / define.
(print_operand): Add 'N' modifier.
* sh.h (VECTOR_MODE_SUPPORTED_P): Add SHmedia vector modes.
(EXTRA_CONSTRAINT_U, EXTRA_CONSTRAINT_W): New macros.
(EXTRA_CONSTRAINT): Add 'U' and 'W' cases.
(CONST_COSTS): Add special case for SHmedia AND.
(PREDICATE_CODES): Add and_operand, arith_reg_dest,
extend_reg_operand, extend_reg_or_0_operand, mextr_bit_offset,
sh_const_vec, sh_1el_vec, sh_rep_vec, zero_vec_operand.
target_operand can also be const or unspec.
* sh.md (UNSPEC_INIT_TRAMP, UNSPEC_FCOSA UNSPEC_FSRRA): New constants.
(UNSPEC_FSINA, UNSPEC_NSB, UNSPEC_ALLOCO): Likewise.
(attribute type): Add new types.
(anddi3): Add splitter.
(movdi_const_16bit+1): Add code to handle vector constants and
bitmasks efficiently.
(shori_media): Have generator function made.
(movv8qi, movv8qi_i, movv8qi_i+1, movv8qi_i+2): New patterns.
(movv8qi_i+3, movv2hi, movv2hi_i, movv4hi, movv4hi_i): Likewise.
(movv2si, movv2si_i, absv2si2, absv4hi2, addv2si3, addv4hi3): Likewise.
(ssaddv2si3, usaddv8qi3, ssaddv4hi3, negcmpeqv8qi): Likewise.
(negcmpeqv2si, negcmpeqv4hi, negcmpgtuv8qi, negcmpgtv2si): Likewise.
(negcmpgtv4hi, mcmv, mcnvs_lw, mcnvs_wb, mcnvs_wub): Likewise.
(mextr_rl, mextr_lr, mextr1, mextr2, mextr3, mextr4, mextr5): Likewise.
(mextr6, mextr7, mmacfx_wl, mmacfx_wl_i, mmacnfx_wl): Likewise.
(mmacnfx_wl_i, mulv2si3, mulv4hi3, mmulfx_l, mmulfx_w): Likewise.
(mmulfxrp_w, mmulhi_wl, mmullo_wl, mmul23_wl, mmul01_wl): Likewise.
(mmulsum_wq, mmulsum_wq_i, mperm_w, mperm_w_little): LIkewise.
(mperm_w_big, mperm_w0, msad_ubq, msad_ubq_i, mshalds_l): Likewise.
(mshalds_w, ashrv2si3, ashrv4hi3, mshards_q, mshfhi_b): Likewise.
(mshflo_b, mshf4_b, mshf0_b, mshfhi_l, mshflo_l, mshf4_l): Likewsie.
(mshf0_l, mshfhi_w, mshflo_w, mshf4_w, mshf0_w, mshfhi_l_di): Likewise.
(mshfhi_l_di_rev, mshflo_l_di, mshflo_l_di_rev): Likewise.
(mshflo_l_di_x, mshflo_l_di_x_rev, ashlv2si3, ashlv4hi3): Likewise.
(lshrv2si3, lshrv4hi3, subv2si3, subv4hi3, sssubv2si3): Likewise.
(ussubv8qi3, sssubv4hi3, fcosa_s, fsina_s, fipr, fsrra_s): Likewise.
(ftrv): Likewise.
(fpu_switch+1, fpu_switch+2): Remove constraint.
2002-07-01 Aldy Hernandez <aldyh@redhat.com>
* tree.c (build_function_type_list): Update function comment.
......
gcc/config/sh/sh.h
......@@ -924,8 +924,11 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
/* Value is 1 if MODE is a supported vector mode. */
#define VECTOR_MODE_SUPPORTED_P(MODE) \
(TARGET_FPU_ANY \
&& ((MODE) == V2SFmode || (MODE) == V4SFmode || (MODE) == V16SFmode))
((TARGET_FPU_ANY \
&& ((MODE) == V2SFmode || (MODE) == V4SFmode || (MODE) == V16SFmode)) \
|| (TARGET_SHMEDIA \
&& ((MODE) == V8QImode || (MODE) == V2HImode || (MODE) == V4HImode \
|| (MODE) == V2SImode)))
/* Value is 1 if it is a good idea to tie two pseudo registers
when one has mode MODE1 and one has mode MODE2.
......@@ -2312,10 +2315,27 @@ while (0)
#define EXTRA_CONSTRAINT_T(OP) \
(NON_PIC_REFERENCE_P (OP))
/* A zero in any shape or form. */
#define EXTRA_CONSTRAINT_U(OP) \
((OP) == const0_rtx \
|| (GET_CODE (OP) == SUBREG && VECTOR_MODE_SUPPORTED_P(GET_MODE (OP)) \
&& SUBREG_REG (OP) == const0_rtx && SUBREG_BYTE (OP) == 0) \
|| GET_CODE (OP) == CONST_VECTOR && zero_vec_operand ((OP), VOIDmode))
/* Any vector constant we can handle. */
#define EXTRA_CONSTRAINT_W(OP) \
(GET_CODE (OP) == CONST_VECTOR \
&& (sh_rep_vec ((OP), VOIDmode) \
|| (HOST_BITS_PER_WIDE_INT >= 64 \
? sh_const_vec ((OP), VOIDmode) \
: sh_1el_vec ((OP), VOIDmode))))
#define EXTRA_CONSTRAINT(OP, C) \
((C) == 'Q' ? EXTRA_CONSTRAINT_Q (OP) \
: (C) == 'S' ? EXTRA_CONSTRAINT_S (OP) \
: (C) == 'T' ? EXTRA_CONSTRAINT_T (OP) \
: (C) == 'U' ? EXTRA_CONSTRAINT_U (OP) \
: (C) == 'W' ? EXTRA_CONSTRAINT_W (OP) \
: 0)
/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
......@@ -2669,6 +2689,8 @@ while (0)
case CONST_INT: \
if (TARGET_SHMEDIA) \
{ \
if ((OUTER_CODE) == AND && and_operand ((RTX), DImode)) \
return 0; \
if (CONST_OK_FOR_J (INTVAL (RTX))) \
return COSTS_N_INSNS (1); \
else if (CONST_OK_FOR_J (INTVAL (RTX) >> 16)) \
......@@ -3188,7 +3210,6 @@ extern int current_function_interrupt;
extern struct rtx_def *sp_switch;
extern int rtx_equal_function_value_matters;
extern struct rtx_def *fpscr_rtx;
/* Instructions with unfilled delay slots take up an
......@@ -3200,23 +3221,32 @@ extern struct rtx_def *fpscr_rtx;
/* Define the codes that are matched by predicates in sh.c. */
#define PREDICATE_CODES \
{"and_operand", {SUBREG, REG, CONST_INT}}, \
{"arith_operand", {SUBREG, REG, CONST_INT}}, \
{"arith_reg_dest", {SUBREG, REG}}, \
{"arith_reg_operand", {SUBREG, REG}}, \
{"arith_reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \
{"binary_float_operator", {PLUS, MULT}}, \
{"commutative_float_operator", {PLUS, MULT}}, \
{"extend_reg_operand", {SUBREG, REG, TRUNCATE}}, \
{"extend_reg_or_0_operand", {SUBREG, REG, TRUNCATE, CONST_INT}}, \
{"fp_arith_reg_operand", {SUBREG, REG}}, \
{"fpscr_operand", {REG}}, \
{"fpul_operand", {REG}}, \
{"general_movsrc_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
{"general_movdst_operand", {SUBREG, REG, MEM}}, \
{"logical_operand", {SUBREG, REG, CONST_INT}}, \
{"mextr_bit_offset", {CONST_INT}}, \
{"noncommutative_float_operator", {MINUS, DIV}}, \
{"shmedia_6bit_operand", {SUBREG, REG, CONST_INT}}, \
{"target_reg_operand", {SUBREG, REG}}, \
{"target_operand", {SUBREG, REG, LABEL_REF, SYMBOL_REF}}, \
{"target_operand", {SUBREG, REG, LABEL_REF, SYMBOL_REF, CONST, UNSPEC}},\
{"register_operand", {SUBREG, REG}}, \
{"symbol_ref_operand", {SYMBOL_REF}},
{"sh_const_vec", {CONST_VECTOR}}, \
{"sh_1el_vec", {CONST_VECTOR, PARALLEL}}, \
{"sh_rep_vec", {CONST_VECTOR, PARALLEL}}, \
{"symbol_ref_operand", {SYMBOL_REF}}, \
{"zero_vec_operand", {CONST_VECTOR}},
/* Define this macro if it is advisable to hold scalars in registers
in a wider mode than that declared by the program. In such cases,
......
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