rs6000.md (move_from_CR_gt_bit): Enable for TARGET_HARD_FLOAT && !TARGET_FPRS, not TARGET_E500.

	* config/rs6000/rs6000.md (move_from_CR_gt_bit): Enable for
	TARGET_HARD_FLOAT && !TARGET_FPRS, not TARGET_E500.
	* config/rs6000/spe.md (e500_cr_ior_compare): Likewise.

testsuite:
	* gcc.target/powerpc/20081204-1.c: New test.

From-SVN: r142477

gcc/ChangeLog

+2008-12-05  Joseph Myers  <joseph@codesourcery.com>
+
+	* config/rs6000/rs6000.md (move_from_CR_gt_bit): Enable for
+	TARGET_HARD_FLOAT && !TARGET_FPRS, not TARGET_E500.
+	* config/rs6000/spe.md (e500_cr_ior_compare): Likewise.
+
 2008-12-05  Jakub Jelinek  <jakub@redhat.com>
 
 	PR tree-optimization/37716

gcc/config/rs6000/rs6000.md

@@ -12215,7 +12215,7 @@
 (define_insn "move_from_CR_gt_bit"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
-  "TARGET_E500"
+  "TARGET_HARD_FLOAT && !TARGET_FPRS"
   "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
   [(set_attr "type" "mfcr")
    (set_attr "length" "8")])

gcc/config/rs6000/spe.md

@@ -3135,7 +3135,7 @@
 	(unspec:CCFP [(match_operand 1 "cc_reg_operand" "y")
 		      (match_operand 2 "cc_reg_operand" "y")]
 		     E500_CR_IOR_COMPARE))]
-  "TARGET_E500"
+  "TARGET_HARD_FLOAT && !TARGET_FPRS"
   "cror 4*%0+gt,4*%1+gt,4*%2+gt"
   [(set_attr "type" "cr_logical")])
 

gcc/testsuite/ChangeLog

+2008-12-05  Joseph Myers  <joseph@codesourcery.com>
+
+	* gcc.target/powerpc/20081204-1.c: New test.
+
 2008-12-05  Richard Guenther  <rguenther@suse.de>
 
 	PR testsuite/38406

gcc/testsuite/gcc.target/powerpc/20081204-1.c

+/* Test for ICE arising from inconsistent use of TARGET_E500 versus
+   TARGET_HARD_FLOAT && !TARGET_FPRS.  */
+/* { dg-do compile } */
+/* { dg-options "-mcpu=750 -mfloat-gprs=single" } */
+static int comp(const void *a,const void *b){
+  return (*(float *)a<*(float *)b)-(*(float *)a>*(float *)b);
+}