re PR target/52941 (SH Target: Add support for movco.l / movli.l atomics on SH4A)

	PR target/52941
	* config/sh/predicates.md (atomic_arith_operand,
	atomic_logical_operand): New predicates.
	* config/sh/sh.c (sh_option_override): Check atomic options.
	* config/sh/sh.h (TARGET_ANY_ATOMIC, UNSUPPORTED_ATOMIC_OPTIONS,
	UNSUPPORTED_HARD_ATOMIC_CPU): New macros.
	(DRIVER_SELF_SPECS): Use UNSUPPORTED_ATOMIC_OPTIONS and
	UNSUPPORTED_HARD_ATOMIC_CPU.
	* config/sh/sync.md: Update description comments.
	(I12): New mode iterator.
	(fetchop_predicate, fetchop_constraint): New code attributes.
	(atomic_compare_and_swapsi_hard, atomic_compare_and_swap<mode>_hard,
	atomic_exchangesi_hard, atomic_exchange<mode>_hard,
	atomic_fetch_<fetchop_name>si_hard,
	atomic_fetch_<fetchop_name><mode>_hard,
	atomic_fetch_nandsi_hard, atomic_fetch_nand<mode>_hard,
	atomic_<fetchop_name>_fetchsi_hard,
	atomic_<fetchop_name>_fetch<mode>_hard,
	atomic_nand_fetchsi_hard, atomic_nand_fetch<mode>_hard,
	atomic_test_and_set_hard): New insns.
	(atomic_compare_and_swap<mode>_soft, atomic_exchange<mode>_soft,
	atomic_fetch_<fetchop_name><mode>_soft, atomic_fetch_nand<mode>_soft,
	atomic_<fetchop_name>_fetch<mode>_soft, atomic_nand_fetch<mode>_soft,
	atomic_test_and_set_soft): Use same formatting for the first line of
	the asm block as in new insns above.
	(atomic_compare_and_swap<mode>, atomic_exchange<mode>,
	atomic_fetch_<fetchop_name><mode>, atomic_<fetchop_name>_fetch<mode>,
	atomic_test_and_set): Integrate new *_hard insns into expanders.
	* config/sh/sh.opt (mhard-atomic): New option.
	* doc/invoke.texi (SH Options): Document it.

From-SVN: r187987

gcc/ChangeLog

+2012-05-29  Oleg Endo  <olegendo@gcc.gnu.org>
+
+	PR target/52941
+	* config/sh/predicates.md (atomic_arith_operand,
+	atomic_logical_operand): New predicates.
+	* config/sh/sh.c (sh_option_override): Check atomic options.
+	* config/sh/sh.h (TARGET_ANY_ATOMIC, UNSUPPORTED_ATOMIC_OPTIONS,
+	UNSUPPORTED_HARD_ATOMIC_CPU): New macros.
+	(DRIVER_SELF_SPECS): Use UNSUPPORTED_ATOMIC_OPTIONS and
+	UNSUPPORTED_HARD_ATOMIC_CPU.
+	* config/sh/sync.md: Update description comments.
+	(I12): New mode iterator.
+	(fetchop_predicate, fetchop_constraint): New code attributes.
+	(atomic_compare_and_swapsi_hard, atomic_compare_and_swap<mode>_hard,
+	atomic_exchangesi_hard, atomic_exchange<mode>_hard,
+	atomic_fetch_<fetchop_name>si_hard,
+	atomic_fetch_<fetchop_name><mode>_hard,
+	atomic_fetch_nandsi_hard, atomic_fetch_nand<mode>_hard,
+	atomic_<fetchop_name>_fetchsi_hard,
+	atomic_<fetchop_name>_fetch<mode>_hard,
+	atomic_nand_fetchsi_hard, atomic_nand_fetch<mode>_hard,
+	atomic_test_and_set_hard): New insns.
+	(atomic_compare_and_swap<mode>_soft, atomic_exchange<mode>_soft,
+	atomic_fetch_<fetchop_name><mode>_soft, atomic_fetch_nand<mode>_soft,
+	atomic_<fetchop_name>_fetch<mode>_soft, atomic_nand_fetch<mode>_soft,
+	atomic_test_and_set_soft): Use same formatting for the first line of
+	the asm block as in new insns above.
+	(atomic_compare_and_swap<mode>, atomic_exchange<mode>,
+	atomic_fetch_<fetchop_name><mode>, atomic_<fetchop_name>_fetch<mode>,
+	atomic_test_and_set): Integrate new *_hard insns into expanders.
+	* config/sh/sh.opt (mhard-atomic): New option.
+	* doc/invoke.texi (SH Options): Document it.
+
 2012-05-29  Meador Inge  <meadori@codesourcery.com>
 
 	* c-decl.c (c_push_function_context): Always create a new language

gcc/config/sh/predicates.md

@@ -879,3 +879,22 @@
     }
   return 0;
 })
+
+;; The atomic_* operand predicates are used for the atomic patterns.
+;; Depending on the particular pattern some operands can be immediate
+;; values.  Using these predicates avoids the usage of 'force_reg' in the
+;; expanders.
+(define_predicate "atomic_arith_operand"
+  (ior (match_code "subreg,reg")
+       (and (match_test "satisfies_constraint_I08 (op)")
+	    (match_test "mode != QImode")
+	    (match_test "mode != HImode")
+	    (match_test "TARGET_SH4A_ARCH"))))
+
+(define_predicate "atomic_logical_operand"
+  (ior (match_code "subreg,reg")
+       (and (match_test "satisfies_constraint_K08 (op)")
+	    (match_test "mode != QImode")
+	    (match_test "mode != HImode")
+	    (match_test "TARGET_SH4A_ARCH"))))
+

gcc/config/sh/sh.c

@@ -882,6 +882,14 @@ sh_option_override (void)
   /* This target defaults to strict volatile bitfields.  */
   if (flag_strict_volatile_bitfields < 0 && abi_version_at_least(2))
     flag_strict_volatile_bitfields = 1;
+
+  /* Make sure that only one atomic mode is selected and that the selection
+     is valid for the current target CPU.  */
+  if (TARGET_SOFT_ATOMIC && TARGET_HARD_ATOMIC)
+    error ("-msoft-atomic and -mhard-atomic cannot be used at the same time");
+  if (TARGET_HARD_ATOMIC && ! TARGET_SH4A_ARCH)
+    error ("-mhard-atomic is only available for SH4A targets");
+
 }
 
 /* Print the operand address in x to the stream.  */

gcc/config/sh/sh.h

@@ -172,6 +172,9 @@ do { \
   (TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5 \
    && ! (TARGET_HITACHI || sh_attr_renesas_p (FUN_DECL)))
 
+/* Nonzero if either soft or hard atomics are enabled.  */
+#define TARGET_ANY_ATOMIC (TARGET_SOFT_ATOMIC | TARGET_HARD_ATOMIC)
+
 #ifndef TARGET_CPU_DEFAULT
 #define TARGET_CPU_DEFAULT SELECT_SH1
 #define SUPPORT_SH1 1
@@ -433,7 +436,20 @@ do { \
 "%{m2a*:%eSH2a does not support little-endian}}"
 #endif
 
-#define DRIVER_SELF_SPECS UNSUPPORTED_SH2A
+#define UNSUPPORTED_ATOMIC_OPTIONS \
+"%{msoft-atomic:%{mhard-atomic:%e-msoft-atomic and -mhard-atomic cannot be \
+used at the same time}}"
+
+#if TARGET_CPU_DEFAULT & MASK_SH4A
+#define UNSUPPORTED_HARD_ATOMIC_CPU ""
+#else
+#define UNSUPPORTED_HARD_ATOMIC_CPU \
+"%{!m4a*:%{mhard-atomic:%e-mhard-atomic is only available for SH4A targets}}"
+#endif
+
+#undef DRIVER_SELF_SPECS
+#define DRIVER_SELF_SPECS UNSUPPORTED_SH2A, UNSUPPORTED_ATOMIC_OPTIONS,\
+			  UNSUPPORTED_HARD_ATOMIC_CPU
 
 #define ASSEMBLER_DIALECT assembler_dialect
 

gcc/config/sh/sh.opt

@@ -321,7 +321,11 @@ Follow Renesas (formerly Hitachi) / SuperH calling conventions
 
 msoft-atomic
 Target Report Var(TARGET_SOFT_ATOMIC)
-Use software atomic sequences supported by kernel
+Use gUSA software atomic sequences
+
+mhard-atomic
+Target Report Var(TARGET_HARD_ATOMIC)
+Use hardware atomic sequences
 
 menable-tas
 Target Report RejectNegative Var(TARGET_ENABLE_TAS)

gcc/doc/invoke.texi

@@ -884,7 +884,7 @@ See RS/6000 and PowerPC Options.
 -mprefergot  -musermode -multcost=@var{number} -mdiv=@var{strategy} @gol
 -mdivsi3_libfunc=@var{name} -mfixed-range=@var{register-range} @gol
 -mindexed-addressing -mgettrcost=@var{number} -mpt-fixed @gol
--maccumulate-outgoing-args -minvalid-symbols -msoft-atomic @gol
+-maccumulate-outgoing-args -minvalid-symbols -msoft-atomic -mhard-atomic @gol
 -mbranch-cost=@var{num} -mcbranchdi -mcmpeqdi -mfused-madd -mpretend-cmove @gol
 -menable-tas}
 
@@ -18054,10 +18054,22 @@ which is incompatible with the SH ABI@.
 Generate GNU/Linux compatible gUSA software atomic sequences for the atomic
 built-in functions.  The generated atomic sequences require support from the 
 interrupt / exception handling code of the system and are only suitable for
-single-core systems.  They will not perform correctly on multi-core systems.
+single-core systems.  They will not operate correctly on multi-core systems.
 This option is enabled by default when the target is @code{sh-*-linux*}.
+When the target is SH4A, this option will also partially utilize the hardware
+atomic instructions @code{movli.l} and @code{movco.l} to create more
+efficient code.
 For details on the atomic built-in functions see @ref{__atomic Builtins}.
 
+@item -mhard-atomic
+@opindex hard-atomic
+Generate hardware atomic sequences for the atomic built-in functions.  This
+is only available on SH4A and is suitable for multi-core systems.  Code
+compiled with this option will also be compatible with gUSA aware
+interrupt / exception handling systems.  In contrast to the
+@option{-msoft-atomic} option this will only use the instructions
+@code{movli.l} and @code{movco.l} to create atomic sequences.
+
 @item -menable-tas
 @opindex menable-tas
 Generate the @code{tas.b} opcode for @code{__atomic_test_and_set}.