irix-csr.c: New file.

	* config/mips/irix-csr.c: New file.
	* config/mips/t-iris6 (irix-csr.o): New rule to build it.
	(EXTRA_MULTILIB_PARTS): Add irix-csr.o.
	* config/mips/iris6.h (ENDFILE_SPEC): Include it in n32 and n64
	executables.

From-SVN: r94186

gcc/ChangeLog

+2005-01-24  Richard Sandiford  <rsandifo@redhat.com>
+
+	* config/mips/irix-csr.c: New file.
+	* config/mips/t-iris6 (irix-csr.o): New rule to build it.
+	(EXTRA_MULTILIB_PARTS): Add irix-csr.o.
+	* config/mips/iris6.h (ENDFILE_SPEC): Include it in n32 and n64
+	executables.
+
 2005-01-24  Eric Botcazou  <ebotcazou@libertysurf.fr>
 
 	PR bootstrap/19364

gcc/config/mips/iris6.h

@@ -97,7 +97,8 @@ Boston, MA 02111-1307, USA.  */
 
 #undef ENDFILE_SPEC
 #define ENDFILE_SPEC \
-  "crtend.o%s irix-crtn.o%s \
+  "%{!shared:%{mabi=n32|mabi=64:irix-csr.o%s}} \
+   crtend.o%s irix-crtn.o%s \
    %{!shared: \
      %{mabi=32:crtn.o%s}\
      %{mabi=n32:%{mips4:/usr/lib32/mips4/crtn.o%s}\

gcc/config/mips/irix-csr.c

+#if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64
+#include <sys/fpu.h>
+
+/* n32 and n64 applications usually run with the MIPS IV Flush to Zero
+   bit set.  Clear it here so that gcc-generated code will handle
+   subnormals correctly by default.  */
+
+static void __attribute__((constructor))
+clear_flush_to_zero (void)
+{
+  union fpc_csr csr;
+
+  csr.fc_word = get_fpc_csr ();
+  csr.fc_struct.flush = 0;
+  set_fpc_csr (csr.fc_word);
+}
+#endif

gcc/config/mips/t-iris6

@@ -19,3 +19,9 @@ tp-bit.c: $(srcdir)/config/fp-bit.c
 	echo '# define TFLOAT' >> tp-bit.c
 	cat $(srcdir)/config/fp-bit.c >> tp-bit.c
 	echo '#endif' >> tp-bit.c
+
+$(T)irix-csr.o: $(srcdir)/config/mips/irix-csr.c $(GCC_PASSES)
+	$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
+	  -c -o $@ $<
+
+EXTRA_MULTILIB_PARTS += irix-csr.o