config.gcc (sh*-*-*): Define SUPPORT_* macros to 1.

	* config.gcc (sh*-*-*): Define SUPPORT_* macros to 1.
	* config/sh/sh.h: Update mask names throughout.
	(target_flags, ISIZE_BIT, DALIGN_BIT, SH1_BIT, SH2_BIT, SH3_BIT)
	(SH_E_BIT, HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, SH4A_BIT, FMOVD_BIT)
	(SH5_BIT, SPACE_BIT, BIGTABLE_BIT, RELAX_BIT, USERMODE_BIT)
	(HITACHI_BIT, NOMACSAVE_BIT, PREFERGOT_BIT, PADSTRUCT_BIT)
	(LITTLE_ENDIAN_BIT, IEEE_BIT, SAVE_ALL_TR_BIT, HARD_SH2A_BIT)
	(HARD_SH2A_DOUBLE_BIT, INDEXED_ADDRESS_BIT, PT_FIXED_BIT)
	(INVALID_SYMBOLS_BIT, ADJUST_UNROLL_BIT, TARGET_DUMPISIZE)
	(TARGET_ALIGN_DOUBLE, TARGET_SH1, TARGET_SH2, TARGET_SH3)
	(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH5, TARGET_FMOVD)
	(TARGET_IEEE, TARGET_SMALLCODE, TARGET_BIGTABLE, TARGET_RELAX)
	(TARGET_HITACHI, TARGET_NOMACSAVE, TARGET_PADSTRUCT)
	(TARGET_LITTLE_ENDIAN, TARGET_USERMODE, TARGET_PREFERGOT)
	(TARGET_SAVE_ALL_TARGET_REGS, TARGET_ALLOW_INDEXED_ADDRESS)
	(TARGET_PT_FIXED, TARGET_INVALID_SYMBOLS, TARGET_ADJUST_UNROLL)
	(TARGET_SWITCH_SH1, TARGET_SWITCH_SH2, TARGET_SWITCH_SH2E)
	(TARGET_SWITCH_SH2A, TARGET_SWITCH_SH2A_SINGLE_ONLY)
	(TARGET_SWITCH_SH2A_SINGLE, TARGET_SWITCH_SH2A_NOFPU)
	(TARGET_SWITCH_SH3, TARGET_SWITCH_SH3E, TARGET_SWITCH_SH4_SINGLE_ONLY)
	(TARGET_SWITCH_SH4_SINGLE, TARGET_SWITCH_SH4_NOFPU, TARGET_SWITCH_SH4)
	(TARGET_SWITCH_SH4A, TARGET_SWITCH_SH4A_SINGLE_ONLY)
	(TARGET_SWITCH_SH4A_SINGLE, TARGET_SWITCH_SH4A_NOFPU)
	(TARGET_SWITCH_SH4AL, TARGET_SWITCH_SH5_64MEDIA)
	(TARGET_SWITCH_SH5_64MEDIA_NOFPU, TARGET_SWITCHES_SH5_32MEDIA)
	(TARGET_SWITCHES_SH5_32MEDIA_NOFPU, TARGET_SWITCH_SH5_32_ANY_EXTRA)
	(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA, TARGET_SWITCHES)
	(SUBTARGET_SWITCHES): Delete.
	(TARGET_SH2E, TARGET_SH2A, TARGET_SH2A_SINGLE, TARGET_SH2A_DOUBLE)
	(TARGET_SH3E, TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARVARD)
	(TARGET_FPU_DOUBLE, TARGET_SH4A_ARCH, TARGET_SHMEDIA32)
	(TARGET_SHMEDIA64): Redefine using other TARGET_* macros.
	(TARGET_SH4): Undefine options.h definition and check MASK_SH1 as well.
	(SUPPORT_SH1, SUPPORT_SH2E, SUPPORT_SH4, SUPPORT_SH4_SINGLE)
	(SUPPORT_SH2A, SUPPORT_SH2A_SINGLE): Make numeric.
	(SUPPORT_SH2): Define to 1 if SUPPORT_SH1.
	(SUPPORT_SH3): Likewise SUPPORT_SH2.
	(SUPPORT_SH4_NOFPU): Likewise SUPPORT_SH3.
	(SUPPORT_SH4A_NOFPU, SUPPORT_SH4AL, SUPPORT_SH2A_NOFPU): Likewise
	SUPPORT_SH4_NOFPU.
	(SUPPORT_SH3E): Likewise SUPPORT_SH2E.
	(SUPPORT_SH4_SINGLE_ONLY, SUPPORT_SH4A_SINGLE_ONLY)
	(SUPPORT_SH2A_SINGLE_ONLY): Likewise SUPPORT_SH3E.
	(SUPPORT_SH4A): Likewise SUPPORT_SH4.
	(SUPPORT_SH4A_SINGLE): Likewise SUPPORT_SH4_SINGLE.
	(SUPPORT_SH5_32MEDIA): Likewise SUPPORT_SH5_COMPACT.
	(SUPPORT_SH5_32MEDIA_NOFPU): Likewise SUPPORT_SH5_COMPACT_NOFPU.
	(SUPPORT_ANY_SH5_32MEDIA, SUPPORT_ANY_SH5_64MEDIA)
	(SUPPORT_ANY_SH5): New macros.
	(TARGET_NONE): Replace with...
	(MASK_ARCH): ...this new macro.
	* config/sh/elf.h: Update mask names
	* config/sh/linux.h: Likewise.
	* config/sh/little.h: Likewise.
	* config/sh/netbsd-elf.h: Likewise.
	* config/sh/symbian-pre.h: Likewise.
	* config/sh/sh.c (sh_handle_option): New function.
	(TARGET_DEFAULT_TARGET_FLAGS, TARGET_HANDLE_OPTION): Override defaults.
	(calc_live_regs): Use MASK_FPU_SINGLE instead of FPU_SINGLE_BIT.
	(sh_target_switches, target_switches): Delete.
	(sh_pch_valid_p): Check for specific differences in the target_flags
	settings.
	(sh_init_cumulative_args): Use MASK_HITACHI instead of HITACHI_BIT.
	* config/sh/sh.opt: New file.

From-SVN: r99916

gcc/ChangeLog

+2005-05-18  Richard Sandiford  <rsandifo@redhat.com>
+
+	* config.gcc (sh*-*-*): Define SUPPORT_* macros to 1.
+	* config/sh/sh.h: Update mask names throughout.
+	(target_flags, ISIZE_BIT, DALIGN_BIT, SH1_BIT, SH2_BIT, SH3_BIT)
+	(SH_E_BIT, HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, SH4A_BIT, FMOVD_BIT)
+	(SH5_BIT, SPACE_BIT, BIGTABLE_BIT, RELAX_BIT, USERMODE_BIT)
+	(HITACHI_BIT, NOMACSAVE_BIT, PREFERGOT_BIT, PADSTRUCT_BIT)
+	(LITTLE_ENDIAN_BIT, IEEE_BIT, SAVE_ALL_TR_BIT, HARD_SH2A_BIT)
+	(HARD_SH2A_DOUBLE_BIT, INDEXED_ADDRESS_BIT, PT_FIXED_BIT)
+	(INVALID_SYMBOLS_BIT, ADJUST_UNROLL_BIT, TARGET_DUMPISIZE)
+	(TARGET_ALIGN_DOUBLE, TARGET_SH1, TARGET_SH2, TARGET_SH3)
+	(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH5, TARGET_FMOVD)
+	(TARGET_IEEE, TARGET_SMALLCODE, TARGET_BIGTABLE, TARGET_RELAX)
+	(TARGET_HITACHI, TARGET_NOMACSAVE, TARGET_PADSTRUCT)
+	(TARGET_LITTLE_ENDIAN, TARGET_USERMODE, TARGET_PREFERGOT)
+	(TARGET_SAVE_ALL_TARGET_REGS, TARGET_ALLOW_INDEXED_ADDRESS)
+	(TARGET_PT_FIXED, TARGET_INVALID_SYMBOLS, TARGET_ADJUST_UNROLL)
+	(TARGET_SWITCH_SH1, TARGET_SWITCH_SH2, TARGET_SWITCH_SH2E)
+	(TARGET_SWITCH_SH2A, TARGET_SWITCH_SH2A_SINGLE_ONLY)
+	(TARGET_SWITCH_SH2A_SINGLE, TARGET_SWITCH_SH2A_NOFPU)
+	(TARGET_SWITCH_SH3, TARGET_SWITCH_SH3E, TARGET_SWITCH_SH4_SINGLE_ONLY)
+	(TARGET_SWITCH_SH4_SINGLE, TARGET_SWITCH_SH4_NOFPU, TARGET_SWITCH_SH4)
+	(TARGET_SWITCH_SH4A, TARGET_SWITCH_SH4A_SINGLE_ONLY)
+	(TARGET_SWITCH_SH4A_SINGLE, TARGET_SWITCH_SH4A_NOFPU)
+	(TARGET_SWITCH_SH4AL, TARGET_SWITCH_SH5_64MEDIA)
+	(TARGET_SWITCH_SH5_64MEDIA_NOFPU, TARGET_SWITCHES_SH5_32MEDIA)
+	(TARGET_SWITCHES_SH5_32MEDIA_NOFPU, TARGET_SWITCH_SH5_32_ANY_EXTRA)
+	(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA, TARGET_SWITCHES)
+	(SUBTARGET_SWITCHES): Delete.
+	(TARGET_SH2E, TARGET_SH2A, TARGET_SH2A_SINGLE, TARGET_SH2A_DOUBLE)
+	(TARGET_SH3E, TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARVARD)
+	(TARGET_FPU_DOUBLE, TARGET_SH4A_ARCH, TARGET_SHMEDIA32)
+	(TARGET_SHMEDIA64): Redefine using other TARGET_* macros.
+	(TARGET_SH4): Undefine options.h definition and check MASK_SH1 as well.
+	(SUPPORT_SH1, SUPPORT_SH2E, SUPPORT_SH4, SUPPORT_SH4_SINGLE)
+	(SUPPORT_SH2A, SUPPORT_SH2A_SINGLE): Make numeric.
+	(SUPPORT_SH2): Define to 1 if SUPPORT_SH1.
+	(SUPPORT_SH3): Likewise SUPPORT_SH2.
+	(SUPPORT_SH4_NOFPU): Likewise SUPPORT_SH3.
+	(SUPPORT_SH4A_NOFPU, SUPPORT_SH4AL, SUPPORT_SH2A_NOFPU): Likewise
+	SUPPORT_SH4_NOFPU.
+	(SUPPORT_SH3E): Likewise SUPPORT_SH2E.
+	(SUPPORT_SH4_SINGLE_ONLY, SUPPORT_SH4A_SINGLE_ONLY)
+	(SUPPORT_SH2A_SINGLE_ONLY): Likewise SUPPORT_SH3E.
+	(SUPPORT_SH4A): Likewise SUPPORT_SH4.
+	(SUPPORT_SH4A_SINGLE): Likewise SUPPORT_SH4_SINGLE.
+	(SUPPORT_SH5_32MEDIA): Likewise SUPPORT_SH5_COMPACT.
+	(SUPPORT_SH5_32MEDIA_NOFPU): Likewise SUPPORT_SH5_COMPACT_NOFPU.
+	(SUPPORT_ANY_SH5_32MEDIA, SUPPORT_ANY_SH5_64MEDIA)
+	(SUPPORT_ANY_SH5): New macros.
+	(TARGET_NONE): Replace with...
+	(MASK_ARCH): ...this new macro.
+	* config/sh/elf.h: Update mask names
+	* config/sh/linux.h: Likewise.
+	* config/sh/little.h: Likewise.
+	* config/sh/netbsd-elf.h: Likewise.
+	* config/sh/symbian-pre.h: Likewise.
+	* config/sh/sh.c (sh_handle_option): New function.
+	(TARGET_DEFAULT_TARGET_FLAGS, TARGET_HANDLE_OPTION): Override defaults.
+	(calc_live_regs): Use MASK_FPU_SINGLE instead of FPU_SINGLE_BIT.
+	(sh_target_switches, target_switches): Delete.
+	(sh_pch_valid_p): Check for specific differences in the target_flags
+	settings.
+	(sh_init_cumulative_args): Use MASK_HITACHI instead of HITACHI_BIT.
+	* config/sh/sh.opt: New file.
+
 2005-05-18  Richard Henderson  <rth@redhat.com>
 
 	PR target/21632

gcc/config.gcc

@@ -1945,7 +1945,7 @@ sh-*-symbianelf* | sh[12346l]*-*-symbianelf* | \
 		sh5-32media | sh5-32media-nofpu | \
 		sh5-compact | sh5-compact-nofpu)
 			tmake_file="${tmake_file} sh/t-mlib-${sh_multilib}"
-			tm_defines="$tm_defines SUPPORT_`echo $sh_multilib|tr a-z- A-Z_`"
+			tm_defines="$tm_defines SUPPORT_`echo $sh_multilib|tr a-z- A-Z_`=1"
 			;;
 		*)
 			echo "with_multilib_list=${sh_multilib} not supported."
@@ -1954,7 +1954,7 @@ sh-*-symbianelf* | sh[12346l]*-*-symbianelf* | \
 		esac
 	done
 	if test x${enable_incomplete_targets} == xyes ; then
-		tm_defines="$tm_defines SUPPORT_SH1 SUPPORT_SH2E SUPPORT_SH4 SUPPORT_SH4_SINGLE SUPPORT_SH2A SUPPORT_SH2A_SINGLE SUPPORT_SH5_32MEDIA SUPPORT_SH5_32MEDIA_NOFPU SUPPORT_SH5_64MEDIA SUPPORT_SH5_64MEDIA_NOFPU"
+		tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1 SUPPORT_SH5_32MEDIA=1 SUPPORT_SH5_32MEDIA_NOFPU=1 SUPPORT_SH5_64MEDIA=1 SUPPORT_SH5_64MEDIA_NOFPU=1"
 	fi
 	use_fixproto=yes
 	;;

gcc/config/sh/elf.h

@@ -61,7 +61,7 @@ Boston, MA 02111-1307, USA.  */
 #undef LINK_SPEC
 #define LINK_SPEC SH_LINK_SPEC
 #undef LINK_EMUL_PREFIX
-#if TARGET_ENDIAN_DEFAULT == LITTLE_ENDIAN_BIT
+#if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
 #define LINK_EMUL_PREFIX "sh%{!mb:l}elf"
 #else
 #define LINK_EMUL_PREFIX "sh%{ml:l}elf"

gcc/config/sh/linux.h

@@ -48,7 +48,7 @@ Boston, MA 02111-1307, USA.  */
 
 #undef TARGET_DEFAULT
 #define TARGET_DEFAULT \
-  (TARGET_CPU_DEFAULT | USERMODE_BIT | TARGET_ENDIAN_DEFAULT \
+  (TARGET_CPU_DEFAULT | MASK_USERMODE | TARGET_ENDIAN_DEFAULT \
    | TARGET_OPT_DEFAULT)
 
 #define TARGET_ASM_FILE_END file_end_indicate_exec_stack

gcc/config/sh/little.h

@@ -19,4 +19,4 @@ along with GCC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
-#define TARGET_ENDIAN_DEFAULT LITTLE_ENDIAN_BIT
+#define TARGET_ENDIAN_DEFAULT MASK_LITTLE_ENDIAN

gcc/config/sh/netbsd-elf.h

@@ -20,21 +20,21 @@ the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
 /* Run-time Target Specification.  */
-#if TARGET_ENDIAN_DEFAULT == LITTLE_ENDIAN_BIT
+#if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
 #define TARGET_VERSION_ENDIAN "le"
 #else
 #define TARGET_VERSION_ENDIAN ""
 #endif
 
-#if TARGET_CPU_DEFAULT & SH5_BIT
-#if TARGET_CPU_DEFAULT & SH_E_BIT
+#if TARGET_CPU_DEFAULT & MASK_SH5
+#if TARGET_CPU_DEFAULT & MASK_SH_E
 #define TARGET_VERSION_CPU "sh5"
 #else
 #define TARGET_VERSION_CPU "sh64"
-#endif /* SH_E_BIT */
+#endif /* MASK_SH_E */
 #else
 #define TARGET_VERSION_CPU "sh"
-#endif /* SH5_BIT */
+#endif /* MASK_SH5 */
 
 #undef TARGET_VERSION
 #define TARGET_VERSION	fprintf (stderr, " (NetBSD/%s%s ELF)",		\
@@ -80,7 +80,7 @@ Boston, MA 02111-1307, USA.  */
 
 #undef TARGET_DEFAULT
 #define TARGET_DEFAULT \
-  (TARGET_CPU_DEFAULT | USERMODE_BIT | TARGET_ENDIAN_DEFAULT)
+  (TARGET_CPU_DEFAULT | MASK_USERMODE | TARGET_ENDIAN_DEFAULT)
 
 /* Define because we use the label and we do not need them.  */
 #define NO_PROFILE_COUNTERS 1

gcc/config/sh/sh.c

@@ -198,6 +198,7 @@ int assembler_dialect;
 
 static bool shmedia_space_reserved_for_target_registers;
 
+static bool sh_handle_option (size_t, const char *, int);
 static void split_branches (rtx);
 static int branch_dest (rtx);
 static void force_into (rtx, rtx);
@@ -325,6 +326,11 @@ static int hard_regs_intersect_p (HARD_REG_SET *, HARD_REG_SET *);
 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
 
+#undef TARGET_DEFAULT_TARGET_FLAGS
+#define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
+#undef TARGET_HANDLE_OPTION
+#define TARGET_HANDLE_OPTION sh_handle_option
+
 #undef TARGET_INSERT_ATTRIBUTES
 #define TARGET_INSERT_ATTRIBUTES sh_insert_attributes
 
@@ -491,6 +497,112 @@ static int hard_regs_intersect_p (HARD_REG_SET *, HARD_REG_SET *);
 
 struct gcc_target targetm = TARGET_INITIALIZER;
 
+/* Implement TARGET_HANDLE_OPTION.  */
+
+static bool
+sh_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED,
+		  int value ATTRIBUTE_UNUSED)
+{
+  switch (code)
+    {
+    case OPT_m1:
+      target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH1;
+      return true;
+
+    case OPT_m2:
+      target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2;
+      return true;
+
+    case OPT_m2a:
+      target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A;
+      return true;
+
+    case OPT_m2a_nofpu:
+      target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_NOFPU;
+      return true;
+
+    case OPT_m2a_single:
+      target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_SINGLE;
+      return true;
+
+    case OPT_m2a_single_only:
+      target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_SINGLE_ONLY;
+      return true;
+
+    case OPT_m2e:
+      target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2E;
+      return true;
+
+    case OPT_m3:
+      target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH3;
+      return true;
+
+    case OPT_m3e:
+      target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH3E;
+      return true;
+
+    case OPT_m4:
+      target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4;
+      return true;
+
+    case OPT_m4_nofpu:
+      target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_NOFPU;
+      return true;
+
+    case OPT_m4_single:
+      target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_SINGLE;
+      return true;
+
+    case OPT_m4_single_only:
+      target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_SINGLE_ONLY;
+      return true;
+
+    case OPT_m4a:
+      target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A;
+      return true;
+
+    case OPT_m4a_nofpu:
+    case OPT_m4al:
+      target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_NOFPU;
+      return true;
+
+    case OPT_m4a_single:
+      target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_SINGLE;
+      return true;
+
+    case OPT_m4a_single_only:
+      target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_SINGLE_ONLY;
+      return true;
+
+    case OPT_m5_32media:
+      target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_32MEDIA;
+      return true;
+
+    case OPT_m5_32media_nofpu:
+      target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_32MEDIA_NOFPU;
+      return true;
+
+    case OPT_m5_64media:
+      target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_64MEDIA;
+      return true;
+
+    case OPT_m5_64media_nofpu:
+      target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_64MEDIA_NOFPU;
+      return true;
+
+    case OPT_m5_compact:
+      target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_COMPACT;
+      return true;
+
+    case OPT_m5_compact_nofpu:
+      target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_COMPACT_NOFPU;
+      return true;
+
+    default:
+      return true;
+    }
+}
+
 /* Print the operand address in x to the stream.  */
 
 void
@@ -5236,7 +5348,7 @@ calc_live_regs (HARD_REG_SET *live_regs_mask)
   CLEAR_HARD_REG_SET (*live_regs_mask);
   if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && interrupt_handler
       && regs_ever_live[FPSCR_REG])
-    target_flags &= ~FPU_SINGLE_BIT;
+    target_flags &= ~MASK_FPU_SINGLE;
   /* If we can save a lot of saves by switching to double mode, do that.  */
   else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && TARGET_FPU_SINGLE)
     for (count = 0, reg = FIRST_FP_REG; reg <= LAST_FP_REG; reg += 2)
@@ -5245,7 +5357,7 @@ calc_live_regs (HARD_REG_SET *live_regs_mask)
 	      || (interrupt_handler && ! pragma_trapa))
 	  && ++count > 2)
 	{
-	  target_flags &= ~FPU_SINGLE_BIT;
+	  target_flags &= ~MASK_FPU_SINGLE;
 	  break;
 	}
   /* PR_MEDIA_REG is a general purpose register, thus global_alloc already
@@ -5327,7 +5439,7 @@ calc_live_regs (HARD_REG_SET *live_regs_mask)
 	      else if (XD_REGISTER_P (reg))
 		{
 		  /* Must switch to double mode to access these registers.  */
-		  target_flags &= ~FPU_SINGLE_BIT;
+		  target_flags &= ~MASK_FPU_SINGLE;
 		}
 	    }
 	}
@@ -7403,17 +7515,7 @@ sh_cfun_interrupt_handler_p (void)
 	  != NULL_TREE);
 }
 
-/* ??? target_switches in toplev.c is static, hence we have to duplicate it.  */
-static const struct
-{
-  const char *const name;
-  const int value;
-  const char *const description;
-}
-sh_target_switches[] = TARGET_SWITCHES;
-#define target_switches sh_target_switches
-
-/* Like default_pch_valid_p, but take flag_mask into account.  */
+/* Like default_pch_valid_p, but only check certain target_flags.  */
 const char *
 sh_pch_valid_p (const void *data_p, size_t len)
 {
@@ -7433,9 +7535,6 @@ sh_pch_valid_p (const void *data_p, size_t len)
   const char *flag_that_differs = NULL;
   size_t i;
   int old_flags;
-  int flag_mask
-    = (SH1_BIT | SH2_BIT | SH3_BIT | SH_E_BIT | HARD_SH4_BIT | FPU_SINGLE_BIT
-       | SH4_BIT | HITACHI_BIT | LITTLE_ENDIAN_BIT);
 
   /* -fpic and -fpie also usually make a PCH invalid.  */
   if (data[0] != flag_pic)
@@ -7446,24 +7545,15 @@ sh_pch_valid_p (const void *data_p, size_t len)
 
   /* Check target_flags.  */
   memcpy (&old_flags, data, sizeof (target_flags));
-  if (((old_flags ^ target_flags) & flag_mask) != 0)
-    {
-      for (i = 0; i < ARRAY_SIZE (target_switches); i++)
-	{
-	  int bits;
+  if ((old_flags ^ target_flags) & (MASK_SH1 | MASK_SH2 | MASK_SH3
+				    | MASK_SH_E | MASK_HARD_SH4
+				    | MASK_FPU_SINGLE | MASK_SH4))
+    return _("created and used with different architectures / ABIs");
+  if ((old_flags ^ target_flags) & MASK_HITACHI)
+    return _("created and used with different ABIs");
+  if ((old_flags ^ target_flags) & MASK_LITTLE_ENDIAN)
+    return _("created and used with different endianness");
 
-	  bits = target_switches[i].value;
-	  if (bits < 0)
-	    bits = -bits;
-	  bits &= flag_mask;
-	  if ((target_flags & bits) != (old_flags & bits))
-	    {
-	      flag_that_differs = target_switches[i].name;
-	      goto make_message;
-	    }
-	}
-      gcc_unreachable ();
-    }
   data += sizeof (target_flags);
   len -= sizeof (target_flags);
 
@@ -10649,7 +10739,7 @@ sh_init_cumulative_args (CUMULATIVE_ARGS *  pcum,
 	     the TYPE or the FNDECL available so we synthesize the
 	     contents of that function as best we can.  */
 	  pcum->force_mem =
-	    (TARGET_DEFAULT & HITACHI_BIT)
+	    (TARGET_DEFAULT & MASK_HITACHI)
 	    && (mode == BLKmode
 		|| (GET_MODE_SIZE (mode) > 4
 		    && !(mode == DFmode

gcc/config/sh/sh.opt

+; Options for the SH port of the compiler.
+
+; Copyright (C) 2005 Free Software Foundation, Inc.
+;
+; This file is part of GCC.
+;
+; GCC is free software; you can redistribute it and/or modify it under
+; the terms of the GNU General Public License as published by the Free
+; Software Foundation; either version 2, or (at your option) any later
+; version.
+;
+; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+; WARRANTY; without even the implied warranty of MERCHANTABILITY or
+; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+; for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with GCC; see the file COPYING.  If not, write to the Free
+; Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+; 02111-1307, USA.
+
+;; Used for various architecture options.
+Mask(SH_E)
+
+;; Set if the default precision of th FPU is single.
+Mask(FPU_SINGLE)
+
+;; Set if we should generate code using type 2A insns.
+Mask(HARD_SH2A)
+
+;; Set if we should generate code using type 2A DF insns.
+Mask(HARD_SH2A_DOUBLE)
+
+;; Set if compiling for SH4 hardware (to be used for insn costs etc.)
+Mask(HARD_SH4)
+
+;; Set if we should generate code for a SH5 CPU (either ISA).
+Mask(SH5)
+
+;; Set if we should save all target registers.
+Mask(SAVE_ALL_TARGET_REGS)
+
+m1
+Target RejectNegative Mask(SH1) Condition(SUPPORT_SH1)
+Generate SH1 code
+
+m2
+Target RejectNegative Mask(SH2) Condition(SUPPORT_SH2)
+Generate SH2 code
+
+m2a
+Target RejectNegative Condition(SUPPORT_SH2A)
+Generate SH2a code
+
+m2a-nofpu
+Target RejectNegative Condition(SUPPORT_SH2A_NOFPU)
+Generate SH2a FPU-less code
+
+m2a-single
+Target RejectNegative Condition (SUPPORT_SH2A_SINGLE)
+Generate default single-precision SH2a code
+
+m2a-single-only
+Target RejectNegative Condition (SUPPORT_SH2A_SINGLE_ONLY)
+Generate only single-precision SH2a code
+
+m2e
+Target RejectNegative Condition(SUPPORT_SH2E)
+Generate SH2e code
+
+m3
+Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3)
+Generate SH3 code
+
+m3e
+Target RejectNegative Condition(SUPPORT_SH3E)
+Generate SH3e code
+
+m4
+Target RejectNegative Mask(SH4) Condition(SUPPORT_SH4)
+Generate SH4 code
+
+m4-nofpu
+Target RejectNegative Condition(SUPPORT_SH4_NOFPU)
+Generate SH4 FPU-less code
+
+m4-single
+Target RejectNegative Condition(SUPPORT_SH4_SINGLE)
+Generate default single-precision SH4 code
+
+m4-single-only
+Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY)
+Generate only single-precision SH4 code
+
+m4a
+Target RejectNegative Mask(SH4A) Condition(SUPPORT_SH4A)
+Generate SH4a code
+
+m4a-nofpu
+Target RejectNegative Condition(SUPPORT_SH4A_NOFPU)
+Generate SH4a FPU-less code
+
+m4a-single
+Target RejectNegative Condition(SUPPORT_SH4A_SINGLE)
+Generate default single-precision SH4a code
+
+m4a-single-only
+Target RejectNegative Condition(SUPPORT_SH4A_SINGLE_ONLY)
+Generate only single-precision SH4a code
+
+m4al
+Target RejectNegative Condition(SUPPORT_SH4AL)
+Generate SH4al-dsp code
+
+m5-32media
+Target RejectNegative Condition(SUPPORT_SH5_32MEDIA)
+Generate 32-bit SHmedia code
+
+m5-32media-nofpu
+Target RejectNegative Condition(SUPPORT_SH5_32MEDIA_NOFPU)
+Generate 32-bit FPU-less SHmedia code
+
+m5-64media
+Target RejectNegative Condition(SUPPORT_SH5_64MEDIA)
+Generate 64-bit SHmedia code
+
+m5-64media-nofpu
+Target RejectNegative Condition(SUPPORT_SH5_64MEDIA_NOFPU)
+Generate 64-bit FPU-less SHmedia code
+
+m5-compact
+Target RejectNegative Condition(SUPPORT_SH5_32MEDIA)
+Generate SHcompact code
+
+m5-compact-nofpu
+Target RejectNegative Condition(SUPPORT_SH5_32MEDIA_NOFPU)
+Generate FPU-less SHcompact code
+
+madjust-unroll
+Target Report Mask(ADJUST_UNROLL) Condition(SUPPORT_ANY_SH5)
+Throttle unrolling to avoid thrashing target registers unless the unroll benefit outweighs this
+
+mb
+Target Report RejectNegative InverseMask(LITTLE_ENDIAN)
+Generate code in big endian mode
+
+mbigtable
+Target Report RejectNegative Mask(BIGTABLE)
+Generate 32-bit offsets in switch tables
+
+mdalign
+Target Report RejectNegative Mask(ALIGN_DOUBLE)
+Align doubles at 64-bit boundaries
+
+mfmovd
+Target RejectNegative Mask(FMOVD) Undocumented
+
+mhitachi
+Target Report RejectNegative Mask(HITACHI)
+Follow Renesas (formerly Hitachi) / SuperH calling conventions
+
+mieee
+Target Report Mask(IEEE)
+Increase the IEEE compliance for floating-point code
+
+mindexed-addressing
+Target Report Mask(ALLOW_INDEXED_ADDRESS) Condition(SUPPORT_ANY_SH5_32MEDIA)
+Enable the use of the indexed addressing mode for SHmedia32/SHcompact
+
+minvalid-symbols
+Target Report Mask(INVALID_SYMBOLS) Condition(SUPPORT_ANY_SH5)
+Assume symbols might be invalid
+
+misize
+Target Report RejectNegative Mask(DUMPISIZE)
+Annotate assembler instructions with estimated addresses
+
+ml
+Target Report RejectNegative Mask(LITTLE_ENDIAN)
+Generate code in little endian mode
+
+mnomacsave
+Target Report RejectNegative Mask(NOMACSAVE)
+Mark MAC register as call-clobbered
+
+;; ??? This option is not useful, but is retained in case there are people
+;; who are still relying on it.  It may be deleted in the future.
+mpadstruct
+Target Report RejectNegative Mask(PADSTRUCT)
+Make structs a multiple of 4 bytes (warning: ABI altered)
+
+mprefergot
+Target Report RejectNegative Mask(PREFERGOT)
+Emit function-calls using global offset table when generating PIC
+
+mpt-fixed
+Target Report Mask(PT_FIXED) Condition(SUPPORT_ANY_SH5)
+Assume pt* instructions won't trap
+
+mrelax
+Target Report RejectNegative Mask(RELAX)
+Shorten address references during linking
+
+mrenesas
+Target Mask(HITACHI) MaskExists
+Follow Renesas (formerly Hitachi) / SuperH calling conventions
+
+mspace
+Target Report RejectNegative Mask(SMALLCODE)
+Deprecated. Use -Os instead
+
+musermode
+Target Report RejectNegative Mask(USERMODE)
+Generate library function call to invalidate instruction cache entries after fixing trampoline

gcc/config/sh/symbian-pre.h

@@ -25,7 +25,7 @@
 #define SYMBIAN		1
 
 /* Default to using the Renesas ABI.  */
-#define TARGET_ABI_DEFAULT	RENESAS_BIT
+#define TARGET_ABI_DEFAULT	MASK_HITACHI
 
 #define SUBTARGET_CPP_SPEC ""