Skip to content

R
riscv-gcc-1
Commit c0600ecd by David Edelsohn Committed by David Edelsohn
Options

rs6000.c (rs6000_rtx_costs): Add EQ, GTU, and LTU. 

	* config/rs6000/rs6000.c (rs6000_rtx_costs): Add EQ, GTU, and LTU.
	* config/rs6000/rs6000.md (sCC): Split GTU and LTU patterns.

From-SVN: r90345
parent 5ae71719
Showing with 121 additions and 50 deletions
gcc/ChangeLog
2004-11-09 David Edelsohn <edelsohn@gnu.org>
* config/rs6000/rs6000.c (rs6000_rtx_costs): Add EQ, GTU, and LTU.
* config/rs6000/rs6000.md (sCC): Split GTU and LTU patterns.
2004-11-09 Kazu Hirata <kazu@cs.umass.edu> 2004-11-09 Kazu Hirata <kazu@cs.umass.edu>
* tree-phinodes.c (phi_reverse): New. * tree-phinodes.c (phi_reverse): New.
......
gcc/config/rs6000/rs6000.c
...@@ -17984,9 +17984,32 @@ rs6000_rtx_costs (rtx x, int code, int outer_code, int *total) ...@@ -17984,9 +17984,32 @@ rs6000_rtx_costs (rtx x, int code, int outer_code, int *total)
*total = rs6000_cost->fp; *total = rs6000_cost->fp;
return false; return false;
} }
break; break;
case EQ:
case GTU:
case LTU:
if (mode == Pmode)
{
switch (outer_code)
{
case PLUS:
case NEG:
/* PLUS or NEG already counted so only add one more. */
*total = COSTS_N_INSNS (1);
break;
case SET:
*total = COSTS_N_INSNS (3);
break;
case COMPARE:
*total = 0;
return true;
default:
break;
}
return false;
}
default: default:
break; break;
} }
......
gcc/config/rs6000/rs6000.md
...@@ -12460,15 +12460,27 @@ ...@@ -12460,15 +12460,27 @@
"doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31" "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
[(set_attr "length" "12")]) [(set_attr "length" "12")])
(define_insn "" (define_insn_and_split ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
"TARGET_32BIT" "TARGET_32BIT"
"@ "#"
{sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0 "TARGET_32BIT"
{ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0" [(set (match_dup 0) (neg:SI (ltu:SI (match_dup 1) (match_dup 2))))
[(set_attr "length" "12")]) (set (match_dup 0) (neg:SI (match_dup 0)))]
"")
(define_insn_and_split ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
(match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))]
"TARGET_64BIT"
"#"
"TARGET_64BIT"
[(set (match_dup 0) (neg:DI (ltu:DI (match_dup 1) (match_dup 2))))
(set (match_dup 0) (neg:DI (match_dup 0)))]
"")
(define_insn "" (define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
...@@ -12503,18 +12515,29 @@ ...@@ -12503,18 +12515,29 @@
(const_int 0)))] (const_int 0)))]
"") "")
(define_insn "" (define_insn_and_split ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P")) (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
(match_operand:SI 3 "reg_or_short_operand" "r,I,r,I")))] (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))]
"TARGET_32BIT" "TARGET_32BIT"
"@ "#"
{sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf|subf} %0,%0,%3 "TARGET_32BIT"
{sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sfi|subfic} %0,%0,%3 [(set (match_dup 0) (neg:SI (ltu:SI (match_dup 1) (match_dup 2))))
{ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf|subf} %0,%0,%3 (set (match_dup 0) (minus:SI (match_dup 3) (match_dup 0)))]
{ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sfi|subfic} %0,%0,%3" "")
[(set_attr "length" "12")])
(define_insn_and_split ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(plus:DI (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
(match_operand:DI 2 "reg_or_neg_short_operand" "r,P"))
(match_operand:DI 3 "reg_or_short_operand" "rI,rI")))]
"TARGET_64BIT"
"#"
"TARGET_64BIT"
[(set (match_dup 0) (neg:DI (ltu:DI (match_dup 1) (match_dup 2))))
(set (match_dup 0) (minus:DI (match_dup 3) (match_dup 0)))]
"")
(define_insn "" (define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
...@@ -12593,7 +12616,19 @@ ...@@ -12593,7 +12616,19 @@
"@ "@
{sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
{ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0" {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
[(set_attr "length" "8")]) [(set_attr "type" "insert_word")
(set_attr "length" "8")])
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(neg:DI (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
(match_operand:DI 2 "reg_or_neg_short_operand" "r,P"))))]
"TARGET_64BIT"
"@
{sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
{ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
[(set_attr "type" "insert_word")
(set_attr "length" "8")])
(define_insn "" (define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r") [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
...@@ -13343,21 +13378,27 @@ ...@@ -13343,21 +13378,27 @@
"doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31" "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
[(set_attr "length" "12")]) [(set_attr "length" "12")])
(define_insn "" (define_insn_and_split ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r") [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI")))] (match_operand:SI 2 "reg_or_short_operand" "rI")))]
"TARGET_32BIT" "TARGET_32BIT"
"{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0" "#"
[(set_attr "length" "12")]) "TARGET_32BIT"
[(set (match_dup 0) (neg:SI (gtu:SI (match_dup 1) (match_dup 2))))
(set (match_dup 0) (neg:SI (match_dup 0)))]
"")
(define_insn "" (define_insn_and_split ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r") [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r") (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
(match_operand:DI 2 "reg_or_short_operand" "rI")))] (match_operand:DI 2 "reg_or_short_operand" "rI")))]
"TARGET_64BIT" "TARGET_64BIT"
"subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg %0,%0" "#"
[(set_attr "length" "12")]) "TARGET_64BIT"
[(set (match_dup 0) (neg:DI (gtu:DI (match_dup 1) (match_dup 2))))
(set (match_dup 0) (neg:DI (match_dup 0)))]
"")
(define_insn "" (define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
...@@ -13421,29 +13462,29 @@ ...@@ -13421,29 +13462,29 @@
(const_int 0)))] (const_int 0)))]
"") "")
(define_insn "" (define_insn_and_split ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r") [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r") (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "I,rI,rI")) (match_operand:SI 2 "reg_or_short_operand" "rI"))
(match_operand:SI 3 "reg_or_short_operand" "r,r,I")))] (match_operand:SI 3 "reg_or_short_operand" "rI")))]
"TARGET_32BIT" "TARGET_32BIT"
"@ "#"
{ai|addic} %0,%1,%k2\;{aze|addze} %0,%3 "TARGET_32BIT"
{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf|subf} %0,%0,%3 [(set (match_dup 0) (neg:SI (gtu:SI (match_dup 1) (match_dup 2))))
{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sfi|subfic} %0,%0,%3" (set (match_dup 0) (minus:SI (match_dup 3) (match_dup 0)))]
[(set_attr "length" "8,12,12")]) "")
(define_insn "" (define_insn_and_split ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,&r") [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r") (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
(match_operand:DI 2 "reg_or_short_operand" "I,rI,rI")) (match_operand:DI 2 "reg_or_short_operand" "rI"))
(match_operand:DI 3 "reg_or_short_operand" "r,r,I")))] (match_operand:DI 3 "reg_or_short_operand" "rI")))]
"TARGET_64BIT" "TARGET_64BIT"
"@ "#"
addic %0,%1,%k2\;addze %0,%3 "TARGET_64BIT"
subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf %0,%0,%3 [(set (match_dup 0) (neg:DI (gtu:DI (match_dup 1) (match_dup 2))))
subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subfic %0,%0,%3" (set (match_dup 0) (minus:DI (match_dup 3) (match_dup 0)))]
[(set_attr "length" "8,12,12")]) "")
(define_insn "" (define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
...@@ -13589,7 +13630,8 @@ ...@@ -13589,7 +13630,8 @@
(match_operand:SI 2 "reg_or_short_operand" "rI"))))] (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
"TARGET_32BIT" "TARGET_32BIT"
"{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0" "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
[(set_attr "length" "8")]) [(set_attr "type" "insert_word")
(set_attr "length" "8")])
(define_insn "" (define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r") [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
...@@ -13597,7 +13639,8 @@ ...@@ -13597,7 +13639,8 @@
(match_operand:DI 2 "reg_or_short_operand" "rI"))))] (match_operand:DI 2 "reg_or_short_operand" "rI"))))]
"TARGET_64BIT" "TARGET_64BIT"
"subf%I2c %0,%1,%2\;subfe %0,%0,%0" "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
[(set_attr "length" "8")]) [(set_attr "type" "insert_word")
(set_attr "length" "8")])
;; Define both directions of branch and return. If we need a reload ;; Define both directions of branch and return. If we need a reload
;; register, we'd rather use CR0 since it is much easier to copy a ;; register, we'd rather use CR0 since it is much easier to copy a
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment