x86: fix vgf2p8affine*qb insns

The affine transformations are not commutative (the two source operands
have entirely different meaning).

Also the nonimmediate_operand predicate can better be vector_operand.

From-SVN: r272783

gcc/ChangeLog

+2019-06-28  Jan Beulich  <jbeulich@suse.com>
+
+	* config/i386/sse.md (vgf2p8affineinvqb_<mode><mask_name>,
+	vgf2p8affineqb_<mode><mask_name>): Drop % constraint modifier.
+	Use vector_operand.
+
 2019-06-28  Claudiu Zissulescu  <claziss@synopsys.com>
 
 	* config/arc/arc.c (arc_rtx_costs): All short instructions are

gcc/config/i386/sse.md

@@ -22112,8 +22112,8 @@
 (define_insn "vgf2p8affineinvqb_<mode><mask_name>"
   [(set (match_operand:VI1_AVX512F 0 "register_operand" "=x,x,v")
 	(unspec:VI1_AVX512F
-	  [(match_operand:VI1_AVX512F 1 "register_operand" "%0,x,v")
-	   (match_operand:VI1_AVX512F 2 "nonimmediate_operand" "xBm,xm,vm")
+	  [(match_operand:VI1_AVX512F 1 "register_operand" "0,x,v")
+	   (match_operand:VI1_AVX512F 2 "vector_operand" "xBm,xm,vm")
 	   (match_operand:QI 3 "const_0_to_255_operand" "n,n,n")]
 	  UNSPEC_GF2P8AFFINEINV))]
   "TARGET_GFNI"
@@ -22130,8 +22130,8 @@
 (define_insn "vgf2p8affineqb_<mode><mask_name>"
   [(set (match_operand:VI1_AVX512F 0 "register_operand" "=x,x,v")
 	(unspec:VI1_AVX512F
-	  [(match_operand:VI1_AVX512F 1 "register_operand" "%0,x,v")
-	   (match_operand:VI1_AVX512F 2 "nonimmediate_operand" "xBm,xm,vm")
+	  [(match_operand:VI1_AVX512F 1 "register_operand" "0,x,v")
+	   (match_operand:VI1_AVX512F 2 "vector_operand" "xBm,xm,vm")
 	   (match_operand:QI 3 "const_0_to_255_operand" "n,n,n")]
 	  UNSPEC_GF2P8AFFINE))]
   "TARGET_GFNI"

gcc/testsuite/ChangeLog

 2019-06-28  Jan Beulich  <jbeulich@suse.com>
 
+	* gcc.target/i386/gfni-5.c: New.
+
+2019-06-28  Jan Beulich  <jbeulich@suse.com>
+
 	* gcc.target/i386/cvtpd2pi: New.
 
 2019-06-27  Jakub Jelinek  <jakub@redhat.com>

gcc/testsuite/gcc.target/i386/gfni-5.c

+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2 -mgfni" } */
+
+typedef char __attribute__((vector_size(16))) v16qi_t;
+
+v16qi_t test16a (v16qi_t x, v16qi_t a)
+{
+  asm volatile ("" : "+m" (a));
+  return __builtin_ia32_vgf2p8affineqb_v16qi (x, a, 0);
+}
+
+v16qi_t test16b (v16qi_t x, v16qi_t a)
+{
+  asm volatile ("" : "+m" (x));
+  return __builtin_ia32_vgf2p8affineqb_v16qi (x, a, 0);
+}
+
+/* { dg-final { scan-assembler-times "gf2p8affineqb\[ \t].*\\(" 1 } } */
+/* { dg-final { scan-assembler-times "gf2p8affineqb\[ \t].*%xmm.*%xmm" 1 } } */