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lvzhengyang
riscv-gcc-1
Commits
bebc6e07
Commit
bebc6e07
authored
Mar 31, 2009
by
Ramana Radhakrishnan
Committed by
Ramana Radhakrishnan
Mar 31, 2009
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Fix documentation for -mthumb
From-SVN: r145347
parent
6b12efe9
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gcc/ChangeLog
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gcc/doc/invoke.texi
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gcc/ChangeLog
View file @
bebc6e07
2009-03-31 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
PR target/27237
* doc/invoke.texi (ARM Options): Update documentation for -mthumb.
2009-03-31 Richard Guenther <rguenther@suse.de>
PR middle-end/31029
...
...
gcc/doc/invoke.texi
View file @
bebc6e07
...
...
@@ -9223,7 +9223,10 @@ Generate code for the Thumb instruction set. The default is to
use
the
32
-
bit
ARM
instruction
set
.
This
option
automatically
enables
either
16
-
bit
Thumb
-
1
or
mixed
16
/
32
-
bit
Thumb
-
2
instructions
based
on
the
@
option
{-
mcpu
=@
var
{
name
}}
and
@
option
{-
march
=@
var
{
name
}}
options
.
and
@
option
{-
march
=@
var
{
name
}}
options
.
This
option
is
not
passed
to
the
assembler
.
If
you
want
to
force
assembler
files
to
be
interpreted
as
Thumb
code
,
either
add
a
@
samp
{.
thumb
}
directive
to
the
source
or
pass
the
@
option
{-
mthumb
}
option
directly
to
the
assembler
by
prefixing
it
with
@
option
{-
Wa
}.
@
item
-
mtpcs
-
frame
@
opindex
mtpcs
-
frame
...
...
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