Skip to content
Projects
Groups
Snippets
Help
This project
Loading...
Sign in / Register
Toggle navigation
R
riscv-gcc-1
Overview
Overview
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Charts
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
lvzhengyang
riscv-gcc-1
Commits
be77d9e7
Commit
be77d9e7
authored
Jan 30, 2004
by
Fariborz Jahanian
Committed by
Fariborz Jahanian
Jan 30, 2004
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
Remove #if 0. Copy operands[1] to pseudo for simplify_gen_subreg.
OKed by David Edehlson. From-SVN: r76984
parent
f0cad2d5
Hide whitespace changes
Inline
Side-by-side
Showing
2 changed files
with
7 additions
and
3 deletions
+7
-3
gcc/ChangeLog
+5
-0
gcc/config/rs6000/rs6000.c
+2
-3
No files found.
gcc/ChangeLog
View file @
be77d9e7
2004-01-30 Fariborz Jahanian <fjahanian@apple.com>
* config/rs6000/rs6000.c (rs6000_emit_move): Remove #if 0.
Copy operands[1] to pseudo for simplify_gen_subreg.
2004-01-30 Kazu Hirata <kazu@cs.umass.edu>
2004-01-30 Kazu Hirata <kazu@cs.umass.edu>
* gcse.c (bypass_block): Fix a typo in the previous check-in
* gcse.c (bypass_block): Fix a typo in the previous check-in
...
...
gcc/config/rs6000/rs6000.c
View file @
be77d9e7
...
@@ -3426,7 +3426,6 @@ rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
...
@@ -3426,7 +3426,6 @@ rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
adjust_address
(
operands
[
1
],
SImode
,
4
));
adjust_address
(
operands
[
1
],
SImode
,
4
));
return
;
return
;
}
}
#if 0
else
if
(
mode
==
DImode
&&
TARGET_POWERPC64
else
if
(
mode
==
DImode
&&
TARGET_POWERPC64
&&
GET_CODE
(
operands
[
0
])
==
REG
&&
GET_CODE
(
operands
[
0
])
==
REG
&&
GET_CODE
(
operands
[
1
])
==
MEM
&&
optimize
>
0
&&
GET_CODE
(
operands
[
1
])
==
MEM
&&
optimize
>
0
...
@@ -3462,11 +3461,11 @@ rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
...
@@ -3462,11 +3461,11 @@ rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
gen_rtx_LSHIFTRT
(
DImode
,
operands
[
1
],
GEN_INT
(
32
)));
gen_rtx_LSHIFTRT
(
DImode
,
operands
[
1
],
GEN_INT
(
32
)));
emit_move_insn
(
adjust_address
(
operands
[
0
],
SImode
,
0
),
emit_move_insn
(
adjust_address
(
operands
[
0
],
SImode
,
0
),
simplify_gen_subreg
(
SImode
,
reg
,
DImode
,
0
));
simplify_gen_subreg
(
SImode
,
reg
,
DImode
,
0
));
emit_move_insn
(
reg
,
operands
[
1
]);
emit_move_insn
(
adjust_address
(
operands
[
0
],
SImode
,
4
),
emit_move_insn
(
adjust_address
(
operands
[
0
],
SImode
,
4
),
simplify_gen_subreg (SImode,
operands[1]
, DImode, 0));
simplify_gen_subreg
(
SImode
,
reg
,
DImode
,
0
));
return
;
return
;
}
}
#endif
if
(
!
no_new_pseudos
)
if
(
!
no_new_pseudos
)
{
{
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment