Commit be5de7a1 by Andreas Krebbel Committed by Andreas Krebbel

s390.md ("*cmp<mode>_ccs"): Fix comment mentioning the instructions emitted by the pattern.

2012-01-03  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>

	* config/s390/s390.md ("*cmp<mode>_ccs"): Fix comment mentioning
	the instructions emitted by the pattern.
	("*TDC_insn_<mode>"): Add comment.

From-SVN: r182831
parent 8b3c2951
2012-01-03 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* config/s390/s390.md ("*cmp<mode>_ccs"): Fix comment mentioning
the instructions emitted by the pattern.
("*TDC_insn_<mode>"): Add comment.
2012-01-03 Richard Guenther <rguenther@suse.de> 2012-01-03 Richard Guenther <rguenther@suse.de>
PR middle-end/51730 PR middle-end/51730
...@@ -1010,7 +1010,7 @@ ...@@ -1010,7 +1010,7 @@
[(set_attr "op_type" "RRE") [(set_attr "op_type" "RRE")
(set_attr "type" "fsimp<mode>")]) (set_attr "type" "fsimp<mode>")])
; cxtr, cxbr, cdbr, cebr, cdb, ceb, cxbtr, cdbtr ; cxtr, cxbr, cdtr, cdbr, cebr, cdb, ceb
(define_insn "*cmp<mode>_ccs" (define_insn "*cmp<mode>_ccs"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (match_operand:FP 0 "register_operand" "f,f") (compare (match_operand:FP 0 "register_operand" "f,f")
...@@ -2816,6 +2816,7 @@ ...@@ -2816,6 +2816,7 @@
; is the register to be tested and the second one is the bit mask ; is the register to be tested and the second one is the bit mask
; specifying the required test(s). ; specifying the required test(s).
; ;
; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet
(define_insn "*TDC_insn_<mode>" (define_insn "*TDC_insn_<mode>"
[(set (reg:CCZ CC_REGNUM) [(set (reg:CCZ CC_REGNUM)
(unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f") (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f")
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment