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riscv-gcc-1
Commit bdf423cb by Michael Meissner
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Try to fix inline of fp/int convert 

From-SVN: r12057
parent b34ec578
Showing with 37 additions and 28 deletions
gcc/config/rs6000/rs6000.md
......@@ -2612,68 +2612,77 @@
}")
(define_insn "lshrsi3_power"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_cint_operand" "r,i")))
(clobber (match_scratch:SI 3 "=q,X"))]
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
(lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
(match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
(clobber (match_scratch:SI 3 "=q,X,X"))]
"TARGET_POWER"
"@
sre %0,%1,%2
mr %0,%1
{s%A2i|s%A2wi} %0,%1,%h2")
(define_insn "lshrsi3_no_power"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri")))]
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_cint_operand" "O,ri")))]
"! TARGET_POWER"
"{sr|srw}%I2 %0,%1,%h2")
"@
mr %0,%1
{sr|srw}%I2 %0,%1,%h2")
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
(compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_cint_operand" "r,i"))
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x")
(compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
(match_operand:SI 2 "reg_or_cint_operand" "r,O,i"))
(const_int 0)))
(clobber (match_scratch:SI 3 "=r,r"))
(clobber (match_scratch:SI 4 "=q,X"))]
(clobber (match_scratch:SI 3 "=r,X,r"))
(clobber (match_scratch:SI 4 "=q,X,X"))]
"TARGET_POWER"
"@
sre. %3,%1,%2
mr. %1,%1
{s%A2i.|s%A2wi.} %3,%1,%h2"
[(set_attr "type" "delayed_compare")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
(compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri"))
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
(compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_cint_operand" "O,ri"))
(const_int 0)))
(clobber (match_scratch:SI 3 "=r"))]
(clobber (match_scratch:SI 3 "=X,r"))]
"! TARGET_POWER"
"{sr|srw}%I2. %3,%1,%h2"
"@
mr. %1,%1
{sr|srw}%I2. %3,%1,%h2"
[(set_attr "type" "delayed_compare")])
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
(compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_cint_operand" "r,i"))
[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x")
(compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
(match_operand:SI 2 "reg_or_cint_operand" "r,O,i"))
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
(lshiftrt:SI (match_dup 1) (match_dup 2)))
(clobber (match_scratch:SI 4 "=q,X"))]
(clobber (match_scratch:SI 4 "=q,X,X"))]
"TARGET_POWER"
"@
sre. %0,%1,%2
mr. %0,%1
{s%A2i.|s%A2wi.} %0,%1,%h2"
[(set_attr "type" "delayed_compare")])
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
(compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri"))
[(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
(compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_cint_operand" "O,ri"))
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(lshiftrt:SI (match_dup 1) (match_dup 2)))]
"! TARGET_POWER"
"{sr|srw}%I2. %0,%1,%h2"
"@
mr. %0,%1
{sr|srw}%I2. %0,%1,%h2"
[(set_attr "type" "delayed_compare")])
(define_insn ""
......
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