Skip to content

R
riscv-gcc-1
Commit bdb60a10 by Michael Meissner Committed by Michael Meissner
Options

rs6000.h (ALTIVEC_VECTOR_MODE): Add IEEE 128-bit floating point modes that can… 

rs6000.h (ALTIVEC_VECTOR_MODE): Add IEEE 128-bit floating point modes that can go in vector registers.

2015-10-29  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/rs6000.h (ALTIVEC_VECTOR_MODE): Add IEEE 128-bit
	floating point modes that can go in vector registers.
	(MODES_TIEABLE_P): Move tests for vector modes before tests for
	scalar floating point, so that IEEE 128-bit floating point that
	can go in vector registers bind with vectors and not FP.
	(struct rs6000_args): Add libcall field.

	* config/rs6000/rs6000.opt (-mfloat128-*): Delete -mfloat128-none
	and -mfloat128-software switches.  Replace them with a binary
	-mfloat128 switch.
	(-mfloat128): Likewise.

	* config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): Allow
	128-bit floating point types in GPRs, even if the appropriate
	option enabling the type was not used.
	(rs6000_debug_reg_global): Remove -mfloat128-{software,none}
	debugging.
	(rs6000_setup_reg_addr_masks): Do not allow pre-increment and
	pre-decrement on IEEE 128-bit floating point values.
	(rs6000_init_hard_regno_mode_ok): Change test for whether TFmode
	is IEEE 128-bit floating point.
	(rs6000_init_hard_regno_mode_ok): Add reload handlers for IEEE
	128-bit floating point types that can go in vector registers.
	(rs6000_option_override_internal): Change -mfloat128-none and
	-mfloat128-software to -mfloat128, and move code to be near other
	VSX option handling.
	(rs6000_option_override_internal): Disable -mfloat128 if we don't
	have the Altivec ABI.
	(rs6000_init_builtins): Don't make TFmode use either IFmode or
	KFmode floating point nodes. Instead, have three separate nodes.
	(rs6000_scalar_mode_supported_p): Add support for IFmode to allow
	eventually moving the long double default to IEEE 128-bit floating
	point.
	(rs6000_opt_masks): Add -mfloat128.
	(struct rs6000_opt_var): Fix typo in comment.
	(init_cumulative_args): Initialize libcall field in
	CUMULATIVE_ARGS.
	(rs6000_function_arg): Treat library functions as if they had
	prototypes to prevent IEEE 128-bit support functions from passing
	arguments in both GPRs and vector registers.
	(rs6000_arg_partial_bytes): Likewise.

	* config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add -mfloat128 as
	an option that can be turned on via -mcpu=<xxx>.

	* config/rs6000/rs6000-opts.h (enum float128_type_t): Delete, no
	longer used.

	* config/rs6000/rs6000-c.c (rs6000_cpu_cpp_builtins): Define
	__FLOAT128__ if -mfloat128. Define __LONG_DOUBLE_IEEE128__ if long
	double is IEEE 128-bit. Define __LONG_DOUBLE_IBM128__ if long
	double is IBM extended double.

	* config/rs6000/predicates.md (reg_or_indexed_operand): Allow
	SUBREGs.

From-SVN: r229545
parent 721be0f4
Showing with 166 additions and 93 deletions
gcc/ChangeLog
2015-10-29 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000.h (ALTIVEC_VECTOR_MODE): Add IEEE 128-bit
floating point modes that can go in vector registers.
(MODES_TIEABLE_P): Move tests for vector modes before tests for
scalar floating point, so that IEEE 128-bit floating point that
can go in vector registers bind with vectors and not FP.
(struct rs6000_args): Add libcall field.
* config/rs6000/rs6000.opt (-mfloat128-*): Delete -mfloat128-none
and -mfloat128-software switches. Replace them with a binary
-mfloat128 switch.
(-mfloat128): Likewise.
* config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): Allow
128-bit floating point types in GPRs, even if the appropriate
option enabling the type was not used.
(rs6000_debug_reg_global): Remove -mfloat128-{software,none}
debugging.
(rs6000_setup_reg_addr_masks): Do not allow pre-increment and
pre-decrement on IEEE 128-bit floating point values.
(rs6000_init_hard_regno_mode_ok): Change test for whether TFmode
is IEEE 128-bit floating point.
(rs6000_init_hard_regno_mode_ok): Add reload handlers for IEEE
128-bit floating point types that can go in vector registers.
(rs6000_option_override_internal): Change -mfloat128-none and
-mfloat128-software to -mfloat128, and move code to be near other
VSX option handling.
(rs6000_option_override_internal): Disable -mfloat128 if we don't
have the Altivec ABI.
(rs6000_init_builtins): Don't make TFmode use either IFmode or
KFmode floating point nodes. Instead, have three separate nodes.
(rs6000_scalar_mode_supported_p): Add support for IFmode to allow
eventually moving the long double default to IEEE 128-bit floating
point.
(rs6000_opt_masks): Add -mfloat128.
(struct rs6000_opt_var): Fix typo in comment.
(init_cumulative_args): Initialize libcall field in
CUMULATIVE_ARGS.
(rs6000_function_arg): Treat library functions as if they had
prototypes to prevent IEEE 128-bit support functions from passing
arguments in both GPRs and vector registers.
(rs6000_arg_partial_bytes): Likewise.
* config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add -mfloat128 as
an option that can be turned on via -mcpu=<xxx>.
* config/rs6000/rs6000-opts.h (enum float128_type_t): Delete, no
longer used.
* config/rs6000/rs6000-c.c (rs6000_cpu_cpp_builtins): Define
__FLOAT128__ if -mfloat128. Define __LONG_DOUBLE_IEEE128__ if long
double is IEEE 128-bit. Define __LONG_DOUBLE_IBM128__ if long
double is IBM extended double.
* config/rs6000/predicates.md (reg_or_indexed_operand): Allow
SUBREGs.
2015-10-29 Mikhail Maltsev <maltsevm@gmail.com>
* genautomata.c: Use CHECKING_P instead of ENABLE_CHECKING.
gcc/config/rs6000/predicates.md
......@@ -684,7 +684,7 @@
;; Like indexed_or_indirect_operand, but also allow a GPR register if direct
;; moves are supported.
(define_predicate "reg_or_indexed_operand"
(match_code "mem,reg")
(match_code "mem,reg,subreg")
{
if (MEM_P (op))
return indexed_or_indirect_operand (op, mode);
......
gcc/config/rs6000/rs6000-c.c
......@@ -408,6 +408,8 @@ rs6000_cpu_cpp_builtins (cpp_reader *pfile)
builtin_define ("__RSQRTE__");
if (TARGET_FRSQRTES)
builtin_define ("__RSQRTEF__");
if (TARGET_FLOAT128)
builtin_define ("__FLOAT128__");
if (TARGET_EXTRA_BUILTINS && cpp_get_options (pfile)->lang != CLK_ASM)
{
......@@ -481,6 +483,11 @@ rs6000_cpu_cpp_builtins (cpp_reader *pfile)
{
builtin_define ("__LONG_DOUBLE_128__");
builtin_define ("__LONGDOUBLE128");
if (TARGET_IEEEQUAD)
builtin_define ("__LONG_DOUBLE_IEEE128__");
else
builtin_define ("__LONG_DOUBLE_IBM128__");
}
switch (TARGET_CMODEL)
......
gcc/config/rs6000/rs6000-cpus.def
......@@ -44,6 +44,7 @@
#define ISA_2_6_MASKS_SERVER (ISA_2_5_MASKS_SERVER \
| OPTION_MASK_POPCNTD \
| OPTION_MASK_ALTIVEC \
| OPTION_MASK_FLOAT128 \
| OPTION_MASK_VSX \
| OPTION_MASK_UPPER_REGS_DF)
......@@ -80,6 +81,7 @@
| OPTION_MASK_DIRECT_MOVE \
| OPTION_MASK_DLMZB \
| OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
| OPTION_MASK_FLOAT128 \
| OPTION_MASK_FPRND \
| OPTION_MASK_HTM \
| OPTION_MASK_ISEL \
......
gcc/config/rs6000/rs6000-opts.h
......@@ -80,14 +80,6 @@ enum fpu_type_t
};
/* Float128 support. */
enum float128_type_t
{
FLOAT128_UNSET = -1, /* Initial value. */
FLOAT128_NONE, /* No __float128 support. */
FLOAT128_SW /* software __float128 support. */
};
/* Types of costly dependences. */
enum rs6000_dependence_cost
{
......
gcc/config/rs6000/rs6000.h
......@@ -1217,11 +1217,16 @@ enum data_align { align_abi, align_opt, align_both };
((MODE) == V4SFmode \
|| (MODE) == V2DFmode) \
#define ALTIVEC_VECTOR_MODE(MODE) \
((MODE) == V16QImode \
|| (MODE) == V8HImode \
|| (MODE) == V4SFmode \
|| (MODE) == V4SImode)
/* Note KFmode and possibly TFmode (i.e. IEEE 128-bit floating point) are not
really a vector, but we want to treat it as a vector for moves, and
such. */
#define ALTIVEC_VECTOR_MODE(MODE) \
((MODE) == V16QImode \
|| (MODE) == V8HImode \
|| (MODE) == V4SFmode \
|| (MODE) == V4SImode \
|| FLOAT128_VECTOR_P (MODE))
#define ALTIVEC_OR_VSX_VECTOR_MODE(MODE) \
(ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \
......@@ -1248,12 +1253,19 @@ enum data_align { align_abi, align_opt, align_both };
PTImode cannot tie with other modes because PTImode is restricted to even
GPR registers, and TImode can go in any GPR as well as VSX registers (PR
57744). */
57744).
Altivec/VSX vector tests were moved ahead of scalar float mode, so that IEEE
128-bit floating point on VSX systems ties with other vectors. */
#define MODES_TIEABLE_P(MODE1, MODE2) \
((MODE1) == PTImode \
? (MODE2) == PTImode \
: (MODE2) == PTImode \
? 0 \
: ALTIVEC_OR_VSX_VECTOR_MODE (MODE1) \
? ALTIVEC_OR_VSX_VECTOR_MODE (MODE2) \
: ALTIVEC_OR_VSX_VECTOR_MODE (MODE2) \
? 0 \
: SCALAR_FLOAT_MODE_P (MODE1) \
? SCALAR_FLOAT_MODE_P (MODE2) \
: SCALAR_FLOAT_MODE_P (MODE2) \
......@@ -1266,10 +1278,6 @@ enum data_align { align_abi, align_opt, align_both };
? SPE_VECTOR_MODE (MODE2) \
: SPE_VECTOR_MODE (MODE2) \
? 0 \
: ALTIVEC_OR_VSX_VECTOR_MODE (MODE1) \
? ALTIVEC_OR_VSX_VECTOR_MODE (MODE2) \
: ALTIVEC_OR_VSX_VECTOR_MODE (MODE2) \
? 0 \
: 1)
/* Post-reload, we can't use any new AltiVec registers, as we already
......@@ -1801,6 +1809,7 @@ typedef struct rs6000_args
GPR space (darwin64) */
int named; /* false for varargs params */
int escapes; /* if function visible outside tu */
int libcall; /* If this is a compiler generated call. */
} CUMULATIVE_ARGS;
/* Initialize a variable CUM of type CUMULATIVE_ARGS
......
gcc/config/rs6000/rs6000.opt
......@@ -601,18 +601,6 @@ moptimize-swaps
Target Undocumented Var(rs6000_optimize_swaps) Init(1) Save
Analyze and remove doubleword swaps from VSX computations.
mfloat128-
Target RejectNegative Joined Enum(float128_type_t) Var(TARGET_FLOAT128) Init(FLOAT128_UNSET) Save
-mfloat128-{software,none} - Specify how IEEE 128-bit floating point is used.
Enum
Name(float128_type_t) Type(enum float128_type_t)
EnumValue
Enum(float128_type_t) String(none) Value(FLOAT128_NONE)
EnumValue
Enum(float128_type_t) String(software) Value(FLOAT128_SW)
EnumValue
Enum(float128_type_t) String(sw) Value(FLOAT128_SW)
mfloat128
Target Report Mask(FLOAT128) Var(rs6000_isa_flags)
Enable/disable IEEE 128-bit floating point via the __float128 keyword.
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment