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riscv-gcc-1
Commit bdb0828f by Richard Earnshaw Committed by Vidya Praveen
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[arm] auto-generate arm-isa.h from CPU descriptions 

This patch autogenerates arm-isa.h from new entries in arm-cpus.in.
This has the primary advantage that it makes the description file more
self-contained, but it also solves the 'array dimensioning' problem
that Tamar recently encountered.  It adds two new constructs to
arm-cpus.in: features and fgroups.  Fgroups are simply a way of naming
a group of feature bits so that they can be referenced together.  We
follow the convention that feature bits are all lower case, while
fgroups are (predominantly) upper case. This is helpful as in some
contexts they share the same namespace. Most of the minor changes in
this patch are related to adopting this new naming convention.

2017-09-22  Richard Earnshaw  <richard.earnshaw@arm.com>

	* config.gcc (arm*-*-*): Don't add arm-isa.h to tm_p_file.
	* config/arm/arm-isa.h: Delete.  Move definitions to ...
	* arm-cpus.in: ... here.  Use new feature and fgroup values.
	* config/arm/arm.c (arm_option_override): Use lower case for feature
	bit names.
	* config/arm/arm.h (TARGET_HARD_FLOAT): Likewise.
	(TARGET_VFP3, TARGET_VFP5, TARGET_FMA): Likewise.
	* config/arm/parsecpu.awk (END): Add new command 'isa'.
	(isa_pfx): Delete.
	(print_isa_bits_for): New function.
	(gen_isa): New function.
	(gen_comm_data): Use print_isa_bits_for.
	(define feature): New keyword.
	(define fgroup): New keyword.
	* config/arm/t-arm (TM_H): Remove.
	(GTM_H): Add arm-isa.h.
	(arm-isa.h): Add rule to generate file.
	* common/config/arm/arm-common.c: (arm_canon_arch_option): Use lower
	case for feature bit names.

From-SVN: r253097
parent 9003adc7
Showing with 186 additions and 258 deletions
gcc/ChangeLog
2017-09-22 Richard Earnshaw <richard.earnshaw@arm.com>
* config.gcc (arm*-*-*): Don't add arm-isa.h to tm_p_file.
* config/arm/arm-isa.h: Delete. Move definitions to ...
* arm-cpus.in: ... here. Use new feature and fgroup values.
* config/arm/arm.c (arm_option_override): Use lower case for feature
bit names.
* config/arm/arm.h (TARGET_HARD_FLOAT): Likewise.
(TARGET_VFP3, TARGET_VFP5, TARGET_FMA): Likewise.
* config/arm/parsecpu.awk (END): Add new command 'isa'.
(isa_pfx): Delete.
(print_isa_bits_for): New function.
(gen_isa): New function.
(gen_comm_data): Use print_isa_bits_for.
(define feature): New keyword.
(define fgroup): New keyword.
* config/arm/t-arm (TM_H): Remove.
(GTM_H): Add arm-isa.h.
(arm-isa.h): Add rule to generate file.
* common/config/arm/arm-common.c: (arm_canon_arch_option): Use lower
case for feature bit names.
2017-09-22 Richard Biener <rguenther@suse.de>
* graphite-isl-ast-to-gimple.c (graphite_verify): Inline into
gcc/common/config/arm/arm-common.c
......@@ -574,7 +574,7 @@ arm_canon_arch_option (int argc, const char **argv)
{
/* The easiest and safest way to remove the default fpu
capabilities is to look for a '+no..' option that removes
the base FPU bit (isa_bit_VFPv2). If that doesn't exist
the base FPU bit (isa_bit_vfpv2). If that doesn't exist
then the best we can do is strip out all the bits that
might be part of the most capable FPU we know about,
which is "crypto-neon-fp-armv8". */
......@@ -586,7 +586,7 @@ arm_canon_arch_option (int argc, const char **argv)
++ext)
{
if (ext->remove
&& check_isa_bits_for (ext->isa_bits, isa_bit_VFPv2))
&& check_isa_bits_for (ext->isa_bits, isa_bit_vfpv2))
{
arm_initialize_isa (fpu_isa, ext->isa_bits);
bitmap_and_compl (target_isa, target_isa, fpu_isa);
......@@ -620,7 +620,7 @@ arm_canon_arch_option (int argc, const char **argv)
{
/* Clearing the VFPv2 bit is sufficient to stop any extention that
builds on the FPU from matching. */
bitmap_clear_bit (target_isa, isa_bit_VFPv2);
bitmap_clear_bit (target_isa, isa_bit_vfpv2);
}
/* If we don't have a selected architecture by now, something's
......@@ -692,8 +692,8 @@ arm_canon_arch_option (int argc, const char **argv)
capable FPU variant that we do support. This is sufficient for
multilib selection. */
if (bitmap_bit_p (target_isa_unsatisfied, isa_bit_VFPv2)
&& bitmap_bit_p (fpu_isa, isa_bit_VFPv2))
if (bitmap_bit_p (target_isa_unsatisfied, isa_bit_vfpv2)
&& bitmap_bit_p (fpu_isa, isa_bit_vfpv2))
{
std::list<candidate_extension *>::iterator ipoint = extensions.begin ();
......
gcc/config.gcc
......@@ -593,7 +593,7 @@ x86_64-*-*)
tm_file="vxworks-dummy.h ${tm_file}"
;;
arm*-*-*)
tm_p_file="arm/arm-flags.h arm/arm-isa.h ${tm_p_file} arm/aarch-common-protos.h"
tm_p_file="arm/arm-flags.h ${tm_p_file} arm/aarch-common-protos.h"
tm_file="vxworks-dummy.h ${tm_file}"
;;
mips*-*-* | sh*-*-* | sparc*-*-*)
......
gcc/config/arm/arm-isa.h deleted 100644 → 0
/* ISA feature bits for ARM.
Copyright (C) 2016-2017 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#ifndef ARM_ISA_FEATURE_H
#define ARM_ISA_FEATURE_H
enum isa_feature
{
isa_nobit, /* Must be first. */
isa_bit_ARMv3m, /* Extended multiply. */
isa_bit_mode26, /* 26-bit mode support. */
isa_bit_mode32, /* 32-bit mode support. */
isa_bit_ARMv4, /* Architecture rel 4. */
isa_bit_ARMv5, /* Architecture rel 5. */
isa_bit_thumb, /* Thumb aware. */
isa_bit_ARMv5e, /* Architecture rel 5e. */
isa_bit_xscale, /* XScale. */
isa_bit_ARMv6, /* Architecture rel 6. */
isa_bit_ARMv6k, /* Architecture rel 6k. */
isa_bit_thumb2, /* Thumb-2. */
isa_bit_notm, /* Instructions not present in 'M' profile. */
isa_bit_be8, /* Architecture uses be8 mode in big-endian. */
isa_bit_tdiv, /* Thumb division instructions. */
isa_bit_ARMv7em, /* Architecture rel 7e-m. */
isa_bit_ARMv7, /* Architecture rel 7. */
isa_bit_adiv, /* ARM division instructions. */
isa_bit_ARMv8, /* Architecture rel 8. */
isa_bit_crc32, /* ARMv8 CRC32 instructions. */
isa_bit_iwmmxt, /* XScale v2 (Wireless MMX). */
isa_bit_iwmmxt2, /* XScale Wireless MMX2. */
isa_bit_ARMv8_1, /* Architecture rel 8.1. */
isa_bit_ARMv8_2, /* Architecutre rel 8.2. */
isa_bit_cmse, /* M-Profile security extensions. */
/* Floating point and Neon extensions. */
/* VFPv1 is not supported in GCC. */
isa_bit_VFPv2, /* Vector floating point v2. */
isa_bit_VFPv3, /* Vector floating point v3. */
isa_bit_VFPv4, /* Vector floating point v4. */
isa_bit_FPv5, /* Floating point v5. */
isa_bit_lpae, /* ARMv7-A LPAE. */
isa_bit_neon, /* Advanced SIMD instructions. */
isa_bit_fp16conv, /* Conversions to/from fp16 (VFPv3 extension). */
isa_bit_fp_dbl, /* Double precision operations supported. */
isa_bit_fp_d32, /* 32 Double precision registers. */
isa_bit_crypto, /* Crypto extension to ARMv8. */
isa_bit_fp16, /* FP16 data processing (half-precision float). */
/* ISA Quirks (errata?). Don't forget to add this to the list of
all quirks below. */
isa_quirk_no_volatile_ce, /* No volatile memory in IT blocks. */
isa_quirk_ARMv6kz, /* Previously mis-identified by GCC. */
isa_quirk_cm3_ldrd, /* Cortex-M3 LDRD quirk. */
/* Aren't currently, but probably should be tuning bits. */
isa_bit_smallmul, /* Slow multiply operations. */
/* Tuning bits. Should be elsewhere. */
isa_tune_co_proc, /* Has co-processor bus. */
isa_tune_ldsched, /* Load scheduling necessary. */
isa_tune_strong, /* StrongARM. */
isa_tune_wbuf, /* Schedule for write buffer ops (ARM6 & 7 only). */
/* Must be last, used to dimension arrays. */
isa_num_bits
};
/* Helper macros for use when defining CPUs and architectures.
There must be no parenthesees in these lists, since they are used
to initialize arrays. */
#define ISA_ARMv2 isa_bit_notm
#define ISA_ARMv3 ISA_ARMv2, isa_bit_mode32
#define ISA_ARMv3m ISA_ARMv3, isa_bit_ARMv3m
#define ISA_ARMv4 ISA_ARMv3m, isa_bit_ARMv4
#define ISA_ARMv4t ISA_ARMv4, isa_bit_thumb
#define ISA_ARMv5 ISA_ARMv4, isa_bit_ARMv5
#define ISA_ARMv5t ISA_ARMv5, isa_bit_thumb
#define ISA_ARMv5e ISA_ARMv5, isa_bit_ARMv5e
#define ISA_ARMv5te ISA_ARMv5e, isa_bit_thumb
#define ISA_ARMv5tej ISA_ARMv5te
#define ISA_ARMv6 ISA_ARMv5te, isa_bit_ARMv6, isa_bit_be8
#define ISA_ARMv6j ISA_ARMv6
#define ISA_ARMv6k ISA_ARMv6, isa_bit_ARMv6k
#define ISA_ARMv6z ISA_ARMv6
#define ISA_ARMv6kz ISA_ARMv6k, isa_quirk_ARMv6kz
#define ISA_ARMv6zk ISA_ARMv6k
#define ISA_ARMv6t2 ISA_ARMv6, isa_bit_thumb2
/* This is suspect. ARMv6-m doesn't really pull in any useful features
from ARMv5* or ARMv6. */
#define ISA_ARMv6m isa_bit_mode32, isa_bit_ARMv3m, isa_bit_ARMv4, \
isa_bit_thumb, isa_bit_ARMv5, isa_bit_ARMv5e, isa_bit_ARMv6
/* This is suspect, the 'common' ARMv7 subset excludes the thumb2 'DSP' and
integer SIMD instructions that are in ARMv6T2. */
#define ISA_ARMv7 ISA_ARMv6m, isa_bit_thumb2, isa_bit_ARMv7
#define ISA_ARMv7a ISA_ARMv7, isa_bit_notm, isa_bit_ARMv6k
#define ISA_ARMv7ve ISA_ARMv7a, isa_bit_adiv, isa_bit_tdiv, isa_bit_lpae
#define ISA_ARMv7r ISA_ARMv7a, isa_bit_tdiv
#define ISA_ARMv7m ISA_ARMv7, isa_bit_tdiv
#define ISA_ARMv7em ISA_ARMv7m, isa_bit_ARMv7em
#define ISA_ARMv8a ISA_ARMv7ve, isa_bit_ARMv8
#define ISA_ARMv8_1a ISA_ARMv8a, isa_bit_crc32, isa_bit_ARMv8_1
#define ISA_ARMv8_2a ISA_ARMv8_1a, isa_bit_ARMv8_2
#define ISA_ARMv8m_base ISA_ARMv6m, isa_bit_ARMv8, isa_bit_cmse, isa_bit_tdiv
#define ISA_ARMv8m_main ISA_ARMv7m, isa_bit_ARMv8, isa_bit_cmse
#define ISA_ARMv8r ISA_ARMv8a
/* List of all cryptographic extensions to stripout if crypto is
disabled. Currently, that's trivial, but we define it anyway for
consistency with the SIMD and FP disable lists. */
#define ISA_ALL_CRYPTO isa_bit_crypto
/* List of all SIMD bits to strip out if SIMD is disabled. This does
strip off 32 D-registers, but does not remove support for
double-precision FP. */
#define ISA_ALL_SIMD isa_bit_fp_d32, isa_bit_neon, ISA_ALL_CRYPTO
/* List of all FPU bits to strip out if -mfpu is used to override the
default. isa_bit_fp16 is deliberately missing from this list. */
#define ISA_ALL_FPU_INTERNAL \
isa_bit_VFPv2, isa_bit_VFPv3, isa_bit_VFPv4, isa_bit_FPv5, \
isa_bit_fp16conv, isa_bit_fp_dbl, ISA_ALL_SIMD
/* Similarly, but including fp16 and other extensions that aren't part of
-mfpu support. */
#define ISA_ALL_FP isa_bit_fp16, ISA_ALL_FPU_INTERNAL
/* Useful combinations. */
#define ISA_VFPv2 isa_bit_VFPv2
#define ISA_VFPv3 ISA_VFPv2, isa_bit_VFPv3
#define ISA_VFPv4 ISA_VFPv3, isa_bit_VFPv4, isa_bit_fp16conv
#define ISA_FPv5 ISA_VFPv4, isa_bit_FPv5
#define ISA_FP_DBL isa_bit_fp_dbl
#define ISA_FP_D32 ISA_FP_DBL, isa_bit_fp_d32
#define ISA_FP_ARMv8 ISA_FPv5, ISA_FP_D32
#define ISA_NEON ISA_FP_D32, isa_bit_neon
#define ISA_CRYPTO ISA_NEON, isa_bit_crypto
/* List of all quirk bits to strip out when comparing CPU features with
architectures. */
#define ISA_ALL_QUIRKS isa_quirk_no_volatile_ce, isa_quirk_ARMv6kz, \
isa_quirk_cm3_ldrd
/* Helper macro so that we can concatenate multiple features together
with arm-*.def files, since macro substitution can't have commas within an
argument that lacks parenthesis. */
#define ISA_FEAT(X) X,
#endif
gcc/config/arm/arm.c
......@@ -3367,22 +3367,22 @@ arm_option_override (void)
/* Initialize boolean versions of the architectural flags, for use
in the arm.md file. */
arm_arch3m = bitmap_bit_p (arm_active_target.isa, isa_bit_ARMv3m);
arm_arch4 = bitmap_bit_p (arm_active_target.isa, isa_bit_ARMv4);
arm_arch3m = bitmap_bit_p (arm_active_target.isa, isa_bit_armv3m);
arm_arch4 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv4);
arm_arch4t = arm_arch4 && bitmap_bit_p (arm_active_target.isa, isa_bit_thumb);
arm_arch5 = bitmap_bit_p (arm_active_target.isa, isa_bit_ARMv5);
arm_arch5e = bitmap_bit_p (arm_active_target.isa, isa_bit_ARMv5e);
arm_arch5 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv5);
arm_arch5e = bitmap_bit_p (arm_active_target.isa, isa_bit_armv5e);
arm_arch5te = arm_arch5e
&& bitmap_bit_p (arm_active_target.isa, isa_bit_thumb);
arm_arch6 = bitmap_bit_p (arm_active_target.isa, isa_bit_ARMv6);
arm_arch6k = bitmap_bit_p (arm_active_target.isa, isa_bit_ARMv6k);
arm_arch6 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv6);
arm_arch6k = bitmap_bit_p (arm_active_target.isa, isa_bit_armv6k);
arm_arch_notm = bitmap_bit_p (arm_active_target.isa, isa_bit_notm);
arm_arch6m = arm_arch6 && !arm_arch_notm;
arm_arch7 = bitmap_bit_p (arm_active_target.isa, isa_bit_ARMv7);
arm_arch7em = bitmap_bit_p (arm_active_target.isa, isa_bit_ARMv7em);
arm_arch8 = bitmap_bit_p (arm_active_target.isa, isa_bit_ARMv8);
arm_arch8_1 = bitmap_bit_p (arm_active_target.isa, isa_bit_ARMv8_1);
arm_arch8_2 = bitmap_bit_p (arm_active_target.isa, isa_bit_ARMv8_2);
arm_arch7 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv7);
arm_arch7em = bitmap_bit_p (arm_active_target.isa, isa_bit_armv7em);
arm_arch8 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv8);
arm_arch8_1 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv8_1);
arm_arch8_2 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv8_2);
arm_arch_thumb1 = bitmap_bit_p (arm_active_target.isa, isa_bit_thumb);
arm_arch_thumb2 = bitmap_bit_p (arm_active_target.isa, isa_bit_thumb2);
arm_arch_xscale = bitmap_bit_p (arm_active_target.isa, isa_bit_xscale);
......@@ -3412,9 +3412,9 @@ arm_option_override (void)
/* And finally, set up some quirks. */
arm_arch_no_volatile_ce
= bitmap_bit_p (arm_active_target.isa, isa_quirk_no_volatile_ce);
arm_arch6kz
= arm_arch6k && bitmap_bit_p (arm_active_target.isa, isa_quirk_ARMv6kz);
= bitmap_bit_p (arm_active_target.isa, isa_bit_quirk_no_volatile_ce);
arm_arch6kz = arm_arch6k && bitmap_bit_p (arm_active_target.isa,
isa_bit_quirk_armv6kz);
/* V5 code we generate is completely interworking capable, so we turn off
TARGET_INTERWORK here to avoid many tests later on. */
......@@ -3459,7 +3459,7 @@ arm_option_override (void)
else if (TARGET_HARD_FLOAT_ABI)
{
arm_pcs_default = ARM_PCS_AAPCS_VFP;
if (!bitmap_bit_p (arm_active_target.isa, isa_bit_VFPv2))
if (!bitmap_bit_p (arm_active_target.isa, isa_bit_vfpv2))
error ("-mfloat-abi=hard: selected processor lacks an FPU");
}
else
......@@ -3562,7 +3562,7 @@ arm_option_override (void)
/* Enable -mfix-cortex-m3-ldrd by default for Cortex-M3 cores. */
if (fix_cm3_ldrd == 2)
{
if (bitmap_bit_p (arm_active_target.isa, isa_quirk_cm3_ldrd))
if (bitmap_bit_p (arm_active_target.isa, isa_bit_quirk_cm3_ldrd))
fix_cm3_ldrd = 1;
else
fix_cm3_ldrd = 0;
......
gcc/config/arm/arm.h
......@@ -122,7 +122,7 @@ extern tree arm_fp16_type_node;
/* Use hardware floating point instructions. */
#define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT \
&& bitmap_bit_p (arm_active_target.isa, \
isa_bit_VFPv2))
isa_bit_vfpv2))
#define TARGET_SOFT_FLOAT (!TARGET_HARD_FLOAT)
/* User has permitted use of FP instructions, if they exist for this
target. */
......@@ -169,10 +169,10 @@ extern tree arm_fp16_type_node;
#define TARGET_VFPD32 (bitmap_bit_p (arm_active_target.isa, isa_bit_fp_d32))
/* FPU supports VFPv3 instructions. */
#define TARGET_VFP3 (bitmap_bit_p (arm_active_target.isa, isa_bit_VFPv3))
#define TARGET_VFP3 (bitmap_bit_p (arm_active_target.isa, isa_bit_vfpv3))
/* FPU supports FPv5 instructions. */
#define TARGET_VFP5 (bitmap_bit_p (arm_active_target.isa, isa_bit_FPv5))
#define TARGET_VFP5 (bitmap_bit_p (arm_active_target.isa, isa_bit_fpv5))
/* FPU only supports VFP single-precision instructions. */
#define TARGET_VFP_SINGLE (!TARGET_VFP_DOUBLE)
......@@ -194,7 +194,7 @@ extern tree arm_fp16_type_node;
(TARGET_HARD_FLOAT && (TARGET_FP16 && TARGET_VFP5))
/* FPU supports fused-multiply-add operations. */
#define TARGET_FMA (bitmap_bit_p (arm_active_target.isa, isa_bit_VFPv4))
#define TARGET_FMA (bitmap_bit_p (arm_active_target.isa, isa_bit_vfpv4))
/* FPU supports Crypto extensions. */
#define TARGET_CRYPTO (bitmap_bit_p (arm_active_target.isa, isa_bit_crypto))
......
gcc/config/arm/parsecpu.awk
......@@ -22,6 +22,7 @@
# data: Print the standard 'C' data tables for the CPUs
# common-data: Print the 'C' data for shared driver/compiler files
# headers: Print the standard 'C' headers for the CPUs
# isa: Generate the arm-isa.h header
# md: Print the machine description fragment
# opt: Print the option tables fragment
# chkcpu <name>: Checks that <name> is a valid CPU
......@@ -83,9 +84,44 @@ function tune_flag_pfx (f) {
return "TF_" f
}
function isa_pfx (f) {
if (f ~ /^(bit|quirk)_.*/) return "isa_" f
return "ISA_" f
# Print out the bits for the features in FLIST, which may be a
# mixture of fgroup and individual bits. Print each feature needed
# exactly once. Terminate the list with isa_nobit. Prefix each line by
# INDENT. Does not print a new line at the end.
function print_isa_bits_for (flist, indent) {
nbits = split (flist, bits)
for (bit = 1; bit <= nbits; bit++) {
if (bits[bit] in features) {
pbit[bits[bit]] = 1
} else if (bits[bit] in fgroup) {
for (gbits in fgrp_bits) {
split (gbits, bitsep, SUBSEP)
if (bitsep[1] == bits[bit]) {
pbit[bitsep[2]] = 1
}
}
} else fatal("feature " bits[bit] " not declared")
}
zbit = ORS
ORS = ""
print indent "{\n" indent " "
ORS = ", "
count = 0
for (bname in pbit) {
print "isa_bit_" bname
count++
if (count == 4) {
count = 0
ORS = ""
print "\n" indent " "
ORS = ", "
}
}
ORS = ""
print "isa_nobit\n" indent "}"
ORS = zbit
delete pbit
}
function gen_headers () {
......@@ -125,6 +161,35 @@ function gen_headers () {
print "};"
}
function gen_isa () {
boilerplate("C")
print "enum isa_feature {"
print " isa_nobit = 0,"
for (fbit in features) {
print " isa_bit_" fbit ","
}
print " isa_num_bits"
print "};\n"
for (fgrp in fgroup) {
print "#define ISA_"fgrp " \\"
z = ORS
ORS = ""
first = 1
for (bitcomb in fgrp_bits) {
split (bitcomb, bitsep, SUBSEP)
if (bitsep[1] == fgrp) {
if (first) {
first = 0
} else print ", \\\n"
print " isa_bit_" bitsep[2]
}
}
ORS = z
print "\n"
}
}
function gen_data () {
boilerplate("C")
......@@ -155,7 +220,6 @@ function gen_data () {
}
print " {TARGET_CPU_arm_none, 0, NULL}"
print "};"
}
function gen_comm_data () {
......@@ -172,8 +236,8 @@ function gen_comm_data () {
print " {"
print " \"" opts[opt] "\", " \
cpu_opt_remove[cpus[n],opts[opt]] ", false,"
print " { " cpu_opt_isa[cpus[n],opts[opt]] ", isa_nobit }"
print " },"
print_isa_bits_for(cpu_opt_isa[cpus[n],opts[opt]], " ")
print "\n },"
}
if (cpus[n] in cpu_optaliases) {
naliases = split (cpu_optaliases[cpus[n]], aliases)
......@@ -188,8 +252,8 @@ function gen_comm_data () {
print " {"
print " \"" aliases[alias] "\", " \
cpu_opt_remove[cpus[n],equiv] ", true, "
print " { " cpu_opt_isa[cpus[n],equiv] ", isa_nobit }"
print " },"
print_isa_bits_for(cpu_opt_isa[cpus[n],equiv], " ")
print "\n },"
}
}
print " { NULL, false, false, {isa_nobit}}"
......@@ -214,8 +278,7 @@ function gen_comm_data () {
if (! (feats[1] in arch_isa)) {
fatal("unknown arch " feats[1] " for cpu " cpus[n])
}
print " {"
print " " arch_isa[feats[1]] ","
all_isa_bits = arch_isa[feats[1]]
for (m = 2; m <= nfeats; m++) {
if (! ((feats[1], feats[m]) in arch_opt_isa)) {
fatal("unknown feature " feats[m] " for architecture " feats[1])
......@@ -223,42 +286,16 @@ function gen_comm_data () {
if (arch_opt_remove[feats[1],feats[m]] == "true") {
fatal("cannot remove features from architecture specs")
}
# The isa_features array that is being initialized here has a length
# of max isa_bit_num, which is the last entry in the enum.
# Logically this means that the number of features is implicitly
# never more than the number of feature bits we have. This is only
# true if we don't emit duplicates here. So keep track of which
# options we have already emitted so we don't emit them twice.
nopts = split (arch_opt_isa[feats[1],feats[m]], opts, ",")
for (i = 1; i <= nopts; i++) {
if (! (opts[i] in seen)) {
print " " opts[i] ","
seen[opts[i]]
}
}
all_isa_bits = all_isa_bits " " arch_opt_isa[feats[1],feats[m]]
}
if (cpus[n] in cpu_fpu) {
nopts = split (fpu_isa[cpu_fpu[cpus[n]]], opts, ",")
for (i = 1; i <= nopts; i++) {
if (! (opts[i] in seen)) {
print " " opts[i] ","
seen[opts[i]]
}
}
all_isa_bits = all_isa_bits " " fpu_isa[cpu_fpu[cpus[n]]]
}
if (cpus[n] in cpu_isa) {
nopts = split (cpu_isa[cpus[n]], opts, ",")
for (i = 1; i <= nopts; i++) {
if (! (opts[i] in seen)) {
print " " opts[i] ","
seen[opts[i]]
}
}
all_isa_bits = all_isa_bits " " cpu_isa[cpus[n]]
}
delete seen
print " isa_nobit"
print " }"
print " },"
print_isa_bits_for(all_isa_bits, " ")
print "\n },"
# arch
print " TARGET_ARCH_" arch_cnames[feats[1]]
print " },"
......@@ -278,8 +315,8 @@ function gen_comm_data () {
print " {"
print " \"" opts[opt] "\", " \
arch_opt_remove[archs[n],opts[opt]] ", false,"
print " { " arch_opt_isa[archs[n],opts[opt]] ", isa_nobit }"
print " },"
print_isa_bits_for(arch_opt_isa[archs[n],opts[opt]], " ")
print "\n },"
}
if (archs[n] in arch_optaliases) {
naliases = split (arch_optaliases[archs[n]], aliases)
......@@ -294,8 +331,8 @@ function gen_comm_data () {
print " {"
print " \"" aliases[alias] "\", " \
arch_opt_remove[archs[n],equiv] ", true, "
print " { " arch_opt_isa[archs[n],equiv] ", isa_nobit }"
print " },"
print_isa_bits_for(arch_opt_isa[archs[n],equiv], " ")
print "\n },"
}
}
print " { NULL, false, false, {isa_nobit}}"
......@@ -321,10 +358,8 @@ function gen_comm_data () {
print " arch_opttab_" arch_cnames[archs[n]] ","
} else print " NULL,"
# common.isa_bits
print " {"
print " " arch_isa[archs[n]] ","
print " isa_nobit"
print " },"
print_isa_bits_for(arch_isa[archs[n]], " ")
print ","
# arch, base_arch
print " \"" arch_base[archs[n]] "\", BASE_ARCH_" \
arch_base[archs[n]] ","
......@@ -351,11 +386,8 @@ function gen_comm_data () {
for (n = 1; n <= nfpus; n++) {
print " {"
print " \"" fpus[n] "\","
print " {"
print " " fpu_isa[fpus[n]] ","
print " isa_nobit"
print " }"
print " },"
print_isa_bits_for(fpu_isa[fpus[n]], " ")
print "\n },"
}
print "};"
......@@ -482,6 +514,43 @@ BEGIN {
parse_ok = 1
}
/^define feature / {
if (NF != 3) fatal("syntax: define feature <name>")
toplevel()
fbit = $3
if (fbit in features) fatal("feature " fbit " already defined")
features[fbit] = 1
parse_ok = 1
}
/^define fgroup / {
if (NF < 4) fatal("syntax: define fgroup <name> <feature> [<feature>]*")
toplevel()
fgrp = $3
if (fgrp in fgroup) fatal("feature group " fgrp " already defined")
if (fgrp in features) fatal("feature group " fgrp " aliases a feature")
fcount = NF
for (n = 4; n <= fcount; n++) {
feat = $n
if (feat in features) {
fgrp_bits[fgrp,feat] = 1
} else if (feat in fgroup) {
# fgroups may reference other fgroups, copy their bits
# to our bits. To avoid recursion we don't set fgroup[fgrp]
# until after we have done this, so such attempts will result
# in an invalid group definition.
for (bitcomb in fgrp_bits) {
split (bitcomb, bitsep, SUBSEP)
if (bitsep[1] == feat) {
fgrp_bits[fgrp,bitsep[2]] = 1
}
}
} else fatal("feature group member " feat " unrecognized")
}
fgroup[fgrp] = 1
parse_ok = 1
}
/^begin fpu / {
toplevel()
fpu_name = $3
......@@ -587,8 +656,8 @@ BEGIN {
flag_count = NF
for (n = 2; n <= flag_count; n++) {
if (n == 2) {
flags = isa_pfx($n)
} else flags = flags "," isa_pfx($n)
flags = $n
} else flags = flags " " $n
}
if (cpu_name != "") {
cpu_isa[cpu_name] = flags
......@@ -611,8 +680,8 @@ BEGIN {
flag_count = NF
for (n = 4; n <= flag_count; n++) {
if (n == 4) {
flags = isa_pfx($n)
} else flags = flags "," isa_pfx($n)
flags = $n
} else flags = flags " " $n
}
if (cpu_name != "") {
cpu_opts[cpu_name] = cpu_opts[cpu_name] " " name
......@@ -669,6 +738,8 @@ END {
gen_comm_data()
} else if (cmd == "headers") {
gen_headers()
} else if (cmd == "isa") {
gen_isa()
} else if (cmd == "md") {
gen_md()
} else if (cmd == "opt") {
......
gcc/config/arm/t-arm
......@@ -18,8 +18,7 @@
# along with GCC; see the file COPYING3. If not see
# <http://www.gnu.org/licenses/>.
TM_H += arm-cpu.h
GTM_H += arm-cpu.h
GTM_H += arm-cpu.h arm-isa.h
# All md files - except for arm.md.
# This list should be kept in alphabetical order and updated whenever an md
......@@ -87,6 +86,14 @@ s-arm-cpu: $(srcdir)/config/arm/parsecpu.awk \
$(SHELL) $(srcdir)/../move-if-change tmp-arm-cpu.h arm-cpu.h
$(STAMP) s-arm-cpu
arm-isa.h: s-arm-isa ; @true
s-arm-isa: $(srcdir)/config/arm/parsecpu.awk \
$(srcdir)/config/arm/arm-cpus.in
$(AWK) -f $(srcdir)/config/arm/parsecpu.awk -v cmd=isa \
$(srcdir)/config/arm/arm-cpus.in > tmp-arm-isa.h
$(SHELL) $(srcdir)/../move-if-change tmp-arm-isa.h arm-isa.h
$(STAMP) s-arm-isa
arm-cpu-data.h: s-arm-data ; @true
s-arm-data: $(srcdir)/config/arm/parsecpu.awk \
$(srcdir)/config/arm/arm-cpus.in
......
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