h8300.c (names_small): Remove "BAD" postfix from %r7 byte registers.

        * h8300/h8300.c (names_small): Remove "BAD" postfix from
        %r7 byte registers.
        (rtx_equal_function_value_matters): Remove extra declaration.
        (output_simode_bld): New function.
        * h8300/h8300.h (NO_FUNCTION_CSE): Do define this.  Register
        pressure makes cse-int function addresses rarely a win.
        (reg_class): Remove unnecessary register classes LONG_REGS,
        SP_REG, SP_AND_G_REGS.
        (REG_CLASS_NAMES): Corresponding changes.
        (REG_CLASS_CONTENTS): Corresponding changes.
        (REGNO_REG_CLASS): Corresponding changes.
        (REG_CLASS_FROM_LETTER): Corresponding chagnes.
        (output_simode_bld): Declare.
        * h8300/h8300.md: Nuke comments for stuff which has been fixed.
        (all patterns): Remove references to register class "a" (SP_REGS)
        which no longer exists.
        (many patterns): Accept auto-inc auto-dec addresses in more cases.
        (zero_extendqisi2): New pattern for the H8/300.
        (zero_extendhisi2): Only use zero_extendhisi2_h8300 when not optimizing.
        (extendhisi2): Only use extendhisi2_h8300 when not optimizing.
        (extendqisi2): New pattern for the H8/300.
        (bitfield related patterns): Completely rewrite.
        (fancy_bclr, fancy_btst): Deleted.  Redundant with new bitfield
        patterns.
        (addhi3 pattern for h8300): Handle case where we can't make matching
        constraints (works around hard to fix reload problem).
        (stack_pointer_manip): Delete.
        (and not patterns): New combiner patterns.

From-SVN: r11902

gcc/config/h8300/h8300.c

@@ -104,7 +104,7 @@ byte_reg (x, b)
 {
   static char *names_small[] =
   {"r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
-   "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7lBAD", "r7hBAD"};
+   "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"};
 
   return names_small[REGNO (x) * 2 + b];
 }
@@ -1545,8 +1545,6 @@ expand_a_shift (mode, code, operands)
      int code;
      rtx operands[];
 {
-  extern int rtx_equal_function_value_matters;
-
   emit_move_insn (operands[0], operands[1]);
 
   /* need a loop to get all the bits we want  - we generate the
@@ -2229,3 +2227,29 @@ h8300_valid_machine_decl_attribute (decl, attributes, attr, args)
   return 0;
 }
 
+char *
+output_simode_bld (bild, log2, operands)
+     int bild;
+     int log2;
+     rtx operands[];
+{
+  /* Clear the destination register.  */
+  if (TARGET_H8300H)
+    output_asm_insn ("sub.l\t%S0,%S0", operands);
+  else
+    output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
+
+  /* Get the bit number we want to load.  */
+  if (log2)
+    operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));
+
+  /* Now output the bit load or bit inverse load, and store it in
+     the destination.  */
+  if (bild)
+    output_asm_insn ("bild\t%Z2,%Y1\n\tbst\t#0,%w0", operands);
+  else
+    output_asm_insn ("bld\t%Z2,%Y1\n\tbst\t#0,%w0", operands);
+
+  /* All done.  */
+  return "";
+}

gcc/config/h8300/h8300.h

@@ -125,8 +125,12 @@ do {				\
 /* Define this if addresses of constant functions
    shouldn't be put through pseudo regs where they can be cse'd.
    Desirable on machines where ordinary constants are expensive
-   but a CALL with constant address is cheap.  */
-/* #define NO_FUNCTION_CSE */
+   but a CALL with constant address is cheap. 
+
+   Calls through a register are cheaper than calls to named
+   functions; however, the register pressure this causes makes
+   CSEing of function addresses generally a lose.  */
+#define NO_FUNCTION_CSE 
 
 /* Target machine storage layout */
 
@@ -319,12 +323,8 @@ do {				\
    For any two classes, it is very desirable that there be another
    class that represents their union.  */
    
-/* The h8 has only one kind of register, but we mustn't do byte by
-   byte operations on the sp, so we keep it as a different class */
-
 enum reg_class {
-  NO_REGS, LONG_REGS, GENERAL_REGS, SP_REG, SP_AND_G_REGS,
-  ALL_REGS, LIM_REG_CLASSES
+  NO_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES
 };
 
 #define N_REG_CLASSES (int) LIM_REG_CLASSES
@@ -332,8 +332,7 @@ enum reg_class {
 /* Give names of register classes as strings for dump file.   */
 
 #define REG_CLASS_NAMES \
-{ "NO_REGS", "LONG_REGS", "GENERAL_REGS", "SP_REG", "SP_AND_G_REGS", \
-  "ALL_REGS", "LIM_REGS" }
+{ "NO_REGS", "GENERAL_REGS", "ALL_REGS", "LIM_REGS" }
 
 /* Define which registers fit in which classes.
    This is an initializer for a vector of HARD_REG_SET
@@ -341,22 +340,18 @@ enum reg_class {
 
 #define REG_CLASS_CONTENTS  			\
 {      0,		/* No regs      */	\
-   0x07f,               /* LONG_REGS    */      \
-   0x07f,		/* GENERAL_REGS */	\
-   0x080,		/* SP_REG       */     	\
-   0x0ff,		/* SP_AND_G_REGS */    	\
+   0x0ff,		/* GENERAL_REGS */    	\
    0x1ff,		/* ALL_REGS 	*/	\
 }
 
 /* The same information, inverted:
    Return the class number of the smallest class containing
    reg number REGNO.  This could be a conditional expression
-   or could index an array.  */
+   or could index an array.
 
-#define REGNO_REG_CLASS(REGNO)  \
-   ((REGNO) < 7  ? LONG_REGS  : \
-    (REGNO) == 7 ? SP_REG     : \
-    GENERAL_REGS)
+   ??? What about the ARG_POINTER_REGISTER? */
+
+#define REGNO_REG_CLASS(REGNO)  GENERAL_REGS
 
 /* The class value for index registers, and the one for base regs.  */
 
@@ -365,8 +360,7 @@ enum reg_class {
 
 /* Get reg_class from a letter such as appears in the machine description.  */
 
-#define REG_CLASS_FROM_LETTER(C) \
-  ((C) == 'a' ? (SP_REG) : (C) == 'l' ? (LONG_REGS) : (NO_REGS))
+#define REG_CLASS_FROM_LETTER(C) (NO_REGS)
 
 /* The letters I, J, K, L, M, N, O, P in a register constraint string
    can be used to stand for particular ranges of immediate operands.
@@ -1341,4 +1335,6 @@ do { char dstr[30];					\
 /* Declarations for functions used in insn-output.c.  */
 char *emit_a_shift ();
 int h8300_funcvec_function_p ();
-char *output_adds_subs();
+char *output_adds_subs ();
+char * output_simode_bld ();
+