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lvzhengyang
riscv-gcc-1
Commits
bd3ab23a
Commit
bd3ab23a
authored
Jan 09, 2002
by
Michael Hayes
Committed by
Michael Hayes
Jan 09, 2002
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* config/c4x/c4x/md: Remove extraneous constraints from define_splits.
From-SVN: r48670
parent
21e16bd6
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gcc/ChangeLog
View file @
bd3ab23a
2002-01-09 Michael Hayes <m.hayes@elec.canterbury.ac.nz>
* config/c4x/c4x/md: Remove extraneous constraints from define_splits.
2002-01-08 Richard Henderson <rth@redhat.com>
2002-01-08 Richard Henderson <rth@redhat.com>
* regrename.c (copy_value): Ignore overlapping copies.
* regrename.c (copy_value): Ignore overlapping copies.
...
...
gcc/config/c4x/c4x.md
View file @
bd3ab23a
...
@@ -3420,8 +3420,8 @@
...
@@ -3420,8 +3420,8 @@
; This can generate invalid stack slot displacements
; This can generate invalid stack slot displacements
(define_split
(define_split
[(set (match_operand:QI 0 "reg_operand" "
=r
")
[(set (match_operand:QI 0 "reg_operand" "")
(unspec:QI [(match_operand:QF 1 "reg_operand" "
f
")] 12))]
(unspec:QI [(match_operand:QF 1 "reg_operand" "")] 12))]
"reload_completed"
"reload_completed"
[(set (match_dup 3) (match_dup 1))
[(set (match_dup 3) (match_dup 1))
(set (match_dup 0) (match_dup 2))]
(set (match_dup 0) (match_dup 2))]
...
@@ -3438,8 +3438,8 @@
...
@@ -3438,8 +3438,8 @@
[(set_attr "type" "multi")])
[(set_attr "type" "multi")])
(define_split
(define_split
[(parallel [(set (match_operand:QI 0 "reg_operand" "
=r
")
[(parallel [(set (match_operand:QI 0 "reg_operand" "")
(unspec:QI [(match_operand:QF 1 "reg_operand" "
f
")] 12))
(unspec:QI [(match_operand:QF 1 "reg_operand" "")] 12))
(clobber (reg:CC 21))])]
(clobber (reg:CC 21))])]
"reload_completed"
"reload_completed"
[(set (mem:QF (pre_inc:QI (reg:QI 20)))
[(set (mem:QF (pre_inc:QI (reg:QI 20)))
...
@@ -3473,8 +3473,8 @@
...
@@ -3473,8 +3473,8 @@
; This can generate invalid stack slot displacements
; This can generate invalid stack slot displacements
(define_split
(define_split
[(set (match_operand:QF 0 "reg_operand" "
=f
")
[(set (match_operand:QF 0 "reg_operand" "")
(unspec:QF [(match_operand:QI 1 "reg_operand" "
r
")] 11))]
(unspec:QF [(match_operand:QI 1 "reg_operand" "")] 11))]
"reload_completed"
"reload_completed"
[(set (match_dup 2) (match_dup 1))
[(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (match_dup 3))]
(set (match_dup 0) (match_dup 3))]
...
@@ -3491,8 +3491,8 @@
...
@@ -3491,8 +3491,8 @@
[(set_attr "type" "multi")])
[(set_attr "type" "multi")])
(define_split
(define_split
[(parallel [(set (match_operand:QF 0 "reg_operand" "
=f
")
[(parallel [(set (match_operand:QF 0 "reg_operand" "")
(unspec:QF [(match_operand:QI 1 "reg_operand" "
r
")] 11))
(unspec:QF [(match_operand:QI 1 "reg_operand" "")] 11))
(clobber (reg:CC 21))])]
(clobber (reg:CC 21))])]
"reload_completed"
"reload_completed"
[(set (mem:QI (pre_inc:QI (reg:QI 20)))
[(set (mem:QI (pre_inc:QI (reg:QI 20)))
...
@@ -6428,8 +6428,8 @@
...
@@ -6428,8 +6428,8 @@
[
(set_attr "type" "multi")
]
)
[
(set_attr "type" "multi")
]
)
(define_split
(define_split
[
(set (match_operand:HI 0 "reg_operand" "
=?dc
")
[
(set (match_operand:HI 0 "reg_operand" "")
(sign_extend:HI (match_operand:QI 1 "src_operand" "
rIm
")))
(sign_extend:HI (match_operand:QI 1 "src_operand" "")))
(clobber (reg:CC 21))]
(clobber (reg:CC 21))]
"reload_completed && TARGET_C3X"
"reload_completed && TARGET_C3X"
[
(set (match_dup 2) (match_dup 1))
[
(set (match_dup 2) (match_dup 1))
...
@@ -6440,8 +6440,8 @@
...
@@ -6440,8 +6440,8 @@
operands
[
3
]
= c4x_operand_subword (operands
[
0
]
, 1, 0, HImode);")
operands
[
3
]
= c4x_operand_subword (operands
[
0
]
, 1, 0, HImode);")
(define_split
(define_split
[
(set (match_operand:HI 0 "reg_operand" "
=?dc
")
[
(set (match_operand:HI 0 "reg_operand" "")
(sign_extend:HI (match_operand:QI 1 "src_operand" "
rIm
")))
(sign_extend:HI (match_operand:QI 1 "src_operand" "")))
(clobber (reg:CC 21))]
(clobber (reg:CC 21))]
"reload_completed && ! TARGET_C3X"
"reload_completed && ! TARGET_C3X"
[
(set (match_dup 2) (match_dup 1))
[
(set (match_dup 2) (match_dup 1))
...
@@ -6461,8 +6461,8 @@
...
@@ -6461,8 +6461,8 @@
; If operand0 and operand1 are the same register we don't need
; If operand0 and operand1 are the same register we don't need
; the first set.
; the first set.
(define_split
(define_split
[
(set (match_operand:HI 0 "reg_operand" "
=?dc
")
[
(set (match_operand:HI 0 "reg_operand" "")
(zero_extend:HI (match_operand:QI 1 "src_operand" "
rIm
")))
(zero_extend:HI (match_operand:QI 1 "src_operand" "")))
(clobber (reg:CC 21))]
(clobber (reg:CC 21))]
"reload_completed"
"reload_completed"
[
(set (match_dup 2) (match_dup 1))
[
(set (match_dup 2) (match_dup 1))
...
...
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