[AArch64] Split X-reg UBFX into W-reg LSR when possible

	* config/aarch64/aarch64.md: New define_split above insv<mode>.

	* gcc.target/aarch64/ubfx_lsr_1.c: New test.

From-SVN: r243755

gcc/ChangeLog

+2016-12-16  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* config/aarch64/aarch64.md: New define_split above insv<mode>.
+
 2016-12-16  Jakub Jelinek  <jakub@redhat.com>
 
 	PR c/78408

gcc/config/aarch64/aarch64.md

@@ -4325,6 +4325,26 @@
   [(set_attr "type" "bfx")]
 )
 
+;; When the bit position and width add up to 32 we can use a W-reg LSR
+;; instruction taking advantage of the implicit zero-extension of the X-reg.
+(define_split
+  [(set (match_operand:DI 0 "register_operand")
+	(zero_extract:DI (match_operand:DI 1 "register_operand")
+			 (match_operand 2
+			   "aarch64_simd_shift_imm_offset_di")
+			 (match_operand 3
+			   "aarch64_simd_shift_imm_di")))]
+  "IN_RANGE (INTVAL (operands[2]) + INTVAL (operands[3]), 1,
+	     GET_MODE_BITSIZE (DImode) - 1)
+   && (INTVAL (operands[2]) + INTVAL (operands[3]))
+       == GET_MODE_BITSIZE (SImode)"
+  [(set (match_dup 0)
+	(zero_extend:DI (lshiftrt:SI (match_dup 4) (match_dup 3))))]
+  {
+    operands[4] = gen_lowpart (SImode, operands[1]);
+  }
+)
+
 ;; Bitfield Insert (insv)
 (define_expand "insv<mode>"
   [(set (zero_extract:GPI (match_operand:GPI 0 "register_operand")

gcc/testsuite/ChangeLog

+2016-12-16  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* gcc.target/aarch64/ubfx_lsr_1.c: New test.
+
 2016-12-16  Jakub Jelinek  <jakub@redhat.com>
 
 	PR c/78408

gcc/testsuite/gcc.target/aarch64/ubfx_lsr_1.c

+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+/* Check that an X-reg UBFX can be simplified into a W-reg LSR.  */
+
+int
+f (unsigned long long x)
+{
+  x = (x >> 24) & 255;
+  return x + 1;
+}
+
+/* { dg-final { scan-assembler "lsr\tw" } } */
+/* { dg-final { scan-assembler-not "ubfx\tx" } } */