rs6000.c (mems_ok_for_quad_peep): Rewrite.

2005-08-10  Eric Christopher  <echristo@apple.com>

        * config/rs6000/rs6000.c (mems_ok_for_quad_peep): Rewrite.
        * config/rs6000/rs6000.md (*lfq_power2, *stfq_power2): Use
        V2DFmode.

From-SVN: r102956

gcc/ChangeLog

+2005-08-10  Eric Christopher  <echristo@apple.com>
+
+	* config/rs6000/rs6000.c (mems_ok_for_quad_peep): Rewrite.
+	* config/rs6000/rs6000.md (*lfq_power2, *stfq_power2): Use
+	V2DFmode.
+
 2005-08-10  Andrew Pinski  <pinskia@physics.uc.edu>
 
 	* config/darwin.c (machopic_indirect_data_reference): Use a new register
@@ -74,7 +80,7 @@
 
 2005-08-09  Dorit Nuzman  <dorit@il.ibm.com>
 
-	* tree-vect-transform.c (vect_create_epilog_for_reduction): Set 
+	* tree-vect-transform.c (vect_create_epilog_for_reduction): Set
 	BIT_FIELD_REF_UNSIGNED for newly created BIT_FIELD_REFs.
 
 2005-08-09  Richard Guenther  <rguenther@suse.de>

gcc/config/rs6000/rs6000.md

@@ -4830,7 +4830,7 @@
 			 (match_dup 3)
 			 (match_dup 4)))]
   "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
-   && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)" 
+   && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
   {
      operands[3] = gen_reg_rtx (SFmode);
      operands[4] = gen_reg_rtx (SFmode);
@@ -9144,11 +9144,11 @@
 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
 
 (define_insn "*lfq_power2"
-  [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
-	(match_operand:TF 1 "memory_operand" ""))]
+  [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
+	(match_operand:V2DF 1 "memory_operand" ""))]
   "TARGET_POWER2
    && TARGET_HARD_FLOAT && TARGET_FPRS"
-   "lfq%U1%X1 %0,%1")
+  "lfq%U1%X1 %0,%1")
 
 (define_peephole2
   [(set (match_operand:DF 0 "gpc_reg_operand" "")
@@ -9160,13 +9160,13 @@
    && registers_ok_for_quad_peep (operands[0], operands[2])
    && mems_ok_for_quad_peep (operands[1], operands[3])"
   [(set (match_dup 0)
-        (match_dup 1))]
-  "operands[1] = widen_memory_access (operands[1], TFmode, 0);
-   operands[0] = gen_rtx_REG (TFmode, REGNO (operands[0]));")
+	(match_dup 1))]
+  "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
+   operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
 
 (define_insn "*stfq_power2"
-  [(set (match_operand:TF 0 "memory_operand" "")
-	(match_operand:TF 1 "gpc_reg_operand" "f"))]
+  [(set (match_operand:V2DF 0 "memory_operand" "")
+	(match_operand:V2DF 1 "gpc_reg_operand" "f"))]
   "TARGET_POWER2
    && TARGET_HARD_FLOAT && TARGET_FPRS"
   "stfq%U0%X0 %1,%0")
@@ -9183,8 +9183,8 @@
    && mems_ok_for_quad_peep (operands[0], operands[2])"
   [(set (match_dup 0)
 	(match_dup 1))]
-  "operands[0] = widen_memory_access (operands[0], TFmode, 0);
-   operands[1] = gen_rtx_REG (TFmode, REGNO (operands[1]));")
+  "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
+   operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
 
 ;; after inserting conditional returns we can sometimes have
 ;; unnecessary register moves.  Unfortunately we cannot have a