[Patch ARM] Unified assembler in ARM state.

gcc/ChangeLog:

2015-11-06  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

	* config/arm/arm-ldmstm.ml: Rewrite to generate unified asm templates.
	* config/arm/arm.c (arm_asm_trampoline_template): Make unified asm safe.
	(arm_output_multireg_pop): Likewise.
	(output_move_double):  Likewise.
	(output_move_quad):  Likewise.
	(output_return_instruction): Likewise.
	(arm_print_operand): Remove support for %( and %. print modifiers.
	(arm_output_shift): Make unified asm.
	(arm_declare_function_name): Likewise.
	* config/arm/arm.h (TARGET_UNIFIED_ASM): Delete.
         (ASM_APP_OFF): Adjust.
         (ASM_OUTPUT_REG_PUSH): Undo special casing for TARGET_ARM.
         (ASM_OUTPUT_REG_POP): Likewise.
	* config/arm/arm.md: Adjust uses of %., %(, %) 
	* config/arm/sync.md: Likewise.
	* config/arm/thumb2.md: Likewise.
	* config/arm/ldmstm.md: Regenerate.
	* config/arm/arm.opt (masm-unified-syntax): Do not special case Thumb.
	* doc/invoke.texi (masm-unified-syntax): Update documentation.

gcc/testsuite/ChangeLog:

2015-11-06  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

	* gcc.target/arm/combine-movs.c:
	* gcc.target/arm/interrupt-1.c:
	* gcc.target/arm/interrupt-2.c:
	* gcc.target/arm/unaligned-memcpy-4.c:

From-SVN: r229875

gcc/ChangeLog

+2015-11-06  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
+
+	* config/arm/arm-ldmstm.ml: Rewrite to generate unified asm templates.
+	* config/arm/arm.c (arm_asm_trampoline_template): Make unified asm safe.
+	(arm_output_multireg_pop): Likewise.
+	(output_move_double):  Likewise.
+	(output_move_quad):  Likewise.
+	(output_return_instruction): Likewise.
+	(arm_print_operand): Remove support for %( and %. print modifiers.
+	(arm_output_shift): Make unified asm.
+	(arm_declare_function_name): Likewise.
+	* config/arm/arm.h (TARGET_UNIFIED_ASM): Delete.
+	(ASM_APP_OFF): Adjust.
+	(ASM_OUTPUT_REG_PUSH): Undo special casing for TARGET_ARM.
+	(ASM_OUTPUT_REG_POP): Likewise.
+	* config/arm/arm.md: Adjust uses of %., %(, %)
+	* config/arm/sync.md: Likewise.
+	* config/arm/thumb2.md: Likewise.
+	* config/arm/ldmstm.md: Regenerate.
+	* config/arm/arm.opt (masm-unified-syntax): Do not special case Thumb.
+	* doc/invoke.texi (masm-unified-syntax): Update documentation.
+
 2015-11-06  David Malcolm  <dmalcolm@redhat.com>
 
 	* input.c (dump_line_table_statistics): Dump stats on adhoc table.

gcc/config/arm/arm-ldmstm.ml

@@ -33,9 +33,20 @@ type amode = IA | IB | DA | DB
 
 type optype = IN | OUT | INOUT
 
-let rec string_of_addrmode addrmode =
+let rec string_of_addrmode addrmode thumb update =
+  if thumb || update
+then
   match addrmode with
-    IA -> "ia" | IB -> "ib" | DA -> "da" | DB -> "db"
+    IA -> "ia"
+  | IB -> "ib"
+  | DA -> "da"
+  | DB -> "db"
+else
+  match addrmode with
+    IA -> ""
+  | IB -> "ib"
+  | DA -> "da"
+  | DB -> "db"
 
 let rec initial_offset addrmode nregs =
   match addrmode with
@@ -160,7 +171,7 @@ let target addrmode thumb =
   | _, _ -> raise (InvalidAddrMode "ERROR: Invalid Addressing mode for Thumb1.")
 
 let write_pattern_1 name ls addrmode nregs write_set_fn update thumb =
-  let astr = string_of_addrmode addrmode in
+  let astr = string_of_addrmode addrmode thumb update in
   Printf.printf "(define_insn \"*%s%s%d_%s%s\"\n"
     (if thumb then "thumb_" else "") name nregs astr
     (if update then "_update" else "");
@@ -180,8 +191,10 @@ let write_pattern_1 name ls addrmode nregs write_set_fn update thumb =
   Printf.printf ")]\n  \"%s && XVECLEN (operands[0], 0) == %d\"\n"
     (target addrmode thumb)
     (if update then nregs + 1 else nregs);
-  Printf.printf "  \"%s%%(%s%%)\\t%%%d%s, {"
-    name astr (nregs + 1) (if update then "!" else "");
+  if thumb then
+      Printf.printf "  \"%s%s\\t%%%d%s, {"   name astr (nregs + 1) (if update then "!" else "")
+   else
+      Printf.printf "  \"%s%s%%?\\t%%%d%s, {"  name astr (nregs + 1) (if update then "!" else "");
   for n = 1 to nregs; do
     Printf.printf "%%%d%s" n (if n < nregs then ", " else "")
   done;

gcc/config/arm/arm.h

@@ -237,10 +237,6 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
    && (arm_disable_literal_pool \
        || (!optimize_size && !current_tune->prefer_constant_pool)))
 
-/* We could use unified syntax for arm mode, but for now we just use it
-   for thumb mode.  */
-#define TARGET_UNIFIED_ASM (TARGET_THUMB)
-
 /* Nonzero if this chip provides the DMB instruction.  */
 #define TARGET_HAVE_DMB		(arm_arch6m || arm_arch7)
 
@@ -2023,8 +2019,7 @@ extern int making_const_table;
 		    "\t.syntax divided\n")
 
 #undef  ASM_APP_OFF
-#define ASM_APP_OFF (TARGET_ARM ? "\t.arm\n\t.syntax divided\n" : \
-		     "\t.thumb\n\t.syntax unified\n")
+#define ASM_APP_OFF "\t.syntax unified\n"
 
 /* Output a push or a pop instruction (only used when profiling).
    We can't push STATIC_CHAIN_REGNUM (r12) directly with Thumb-1.  We know
@@ -2035,10 +2030,7 @@ extern int making_const_table;
 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO)		\
   do							\
     {							\
-      if (TARGET_ARM)					\
-	asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n",	\
-		     STACK_POINTER_REGNUM, REGNO);	\
-      else if (TARGET_THUMB1				\
+      if (TARGET_THUMB1					\
 	       && (REGNO) == STATIC_CHAIN_REGNUM)	\
 	{						\
 	  asm_fprintf (STREAM, "\tpush\t{r7}\n");	\
@@ -2054,11 +2046,8 @@ extern int making_const_table;
 #define ASM_OUTPUT_REG_POP(STREAM, REGNO)		\
   do							\
     {							\
-      if (TARGET_ARM)					\
-	asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n",	\
-		     STACK_POINTER_REGNUM, REGNO);	\
-      else if (TARGET_THUMB1				\
-	       && (REGNO) == STATIC_CHAIN_REGNUM)	\
+      if (TARGET_THUMB1					\
+	  && (REGNO) == STATIC_CHAIN_REGNUM)		\
 	{						\
 	  asm_fprintf (STREAM, "\tpop\t{r7}\n");	\
 	  asm_fprintf (STREAM, "\tmov\t%r, r7\n", REGNO);\

gcc/config/arm/arm.opt

@@ -280,4 +280,4 @@ Assume loading data from flash is slower than fetching instructions.
 
 masm-syntax-unified
 Target Report Var(inline_asm_unified) Init(0) Save
-Assume unified syntax for Thumb inline assembly code.
+Assume unified syntax for inline assembly code.

gcc/config/arm/sync.md

@@ -72,7 +72,7 @@
   {
     enum memmodel model = memmodel_from_int (INTVAL (operands[2]));
     if (is_mm_relaxed (model) || is_mm_consume (model) || is_mm_release (model))
-      return \"ldr%(<sync_sfx>%)\\t%0, %1\";
+      return \"ldr<sync_sfx>%?\\t%0, %1\";
     else
       return \"lda<sync_sfx>%?\\t%0, %1\";
   }
@@ -89,7 +89,7 @@
   {
     enum memmodel model = memmodel_from_int (INTVAL (operands[2]));
     if (is_mm_relaxed (model) || is_mm_consume (model) || is_mm_acquire (model))
-      return \"str%(<sync_sfx>%)\t%1, %0\";
+      return \"str<sync_sfx>%?\t%1, %0\";
     else
       return \"stl<sync_sfx>%?\t%1, %0\";
   }

gcc/config/arm/thumb2.md

@@ -330,8 +330,8 @@
    mov%?\\t%0, %1\\t%@ movhi
    mov%?\\t%0, %1\\t%@ movhi
    movw%?\\t%0, %L1\\t%@ movhi
-   str%(h%)\\t%1, %0\\t%@ movhi
-   ldr%(h%)\\t%0, %1\\t%@ movhi"
+   strh%?\\t%1, %0\\t%@ movhi
+   ldrh%?\\t%0, %1\\t%@ movhi"
   [(set_attr "type" "mov_reg,mov_imm,mov_imm,mov_imm,store1,load1")
    (set_attr "predicable" "yes")
    (set_attr "predicable_short_it" "yes,no,yes,no,no,no")
@@ -1028,7 +1028,7 @@
   "TARGET_THUMB2 && arm_arch6"
   "@
    sxtb%?\\t%0, %1
-   ldr%(sb%)\\t%0, %1"
+   ldrsb%?\\t%0, %1"
   [(set_attr "type" "extend,load_byte")
    (set_attr "predicable" "yes")
    (set_attr "predicable_short_it" "no")
@@ -1042,7 +1042,7 @@
   "TARGET_THUMB2 && arm_arch6"
   "@
    uxth%?\\t%0, %1
-   ldr%(h%)\\t%0, %1"
+   ldrh%?\\t%0, %1"
   [(set_attr "type" "extend,load_byte")
    (set_attr "predicable" "yes")
    (set_attr "predicable_short_it" "no")
@@ -1055,8 +1055,8 @@
 	(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
   "TARGET_THUMB2 && arm_arch6"
   "@
-   uxtb%(%)\\t%0, %1
-   ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2"
+   uxtb%?\\t%0, %1
+   ldrb%?\\t%0, %1\\t%@ zero_extendqisi2"
   [(set_attr "type" "extend,load_byte")
    (set_attr "predicable" "yes")
    (set_attr "predicable_short_it" "no")

gcc/doc/invoke.texi

@@ -13757,10 +13757,9 @@ off by default.
 @item -masm-syntax-unified
 @opindex masm-syntax-unified
 Assume inline assembler is using unified asm syntax.  The default is
-currently off which implies divided syntax.  Currently this option is
-available only for Thumb1 and has no effect on ARM state and Thumb2.
-However, this may change in future releases of GCC.  Divided syntax
-should be considered deprecated.
+currently off which implies divided syntax.  This option has no impact
+on Thumb2. However, this may change in future releases of GCC.
+Divided syntax should be considered deprecated.
 
 @item -mrestrict-it
 @opindex mrestrict-it

gcc/testsuite/ChangeLog

+2015-11-06  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
+
+	* gcc.target/arm/combine-movs.c: Adjust for unified asm.
+	* gcc.target/arm/interrupt-1.c: Likewise.
+	* gcc.target/arm/interrupt-2.c: Likewise.
+	* gcc.target/arm/unaligned-memcpy-4.c: Likewise.
+
 2015-11-06  Thomas Schwinge  <thomas@codesourcery.com>
 
 	* gfortran.dg/goacc/combined_loop.f90: XFAIL.

gcc/testsuite/gcc.target/arm/combine-movs.c

@@ -9,5 +9,4 @@ void foo (unsigned long r[], unsigned int d)
     r[i] = 0;
 }
 
-/* { dg-final { scan-assembler "lsrs\tr\[0-9\]" { target arm_thumb2 } } } */
-/* { dg-final { scan-assembler "movs\tr\[0-9\]" { target { ! arm_thumb2 } } } } */
+/* { dg-final { scan-assembler "lsrs\tr\[0-9\]" } } */

gcc/testsuite/gcc.target/arm/interrupt-1.c

@@ -13,5 +13,5 @@ void foo ()
   bar (0);
 }
 
-/* { dg-final { scan-assembler "stmfd\tsp!, {r0, r1, r2, r3, r4, fp, ip, lr}" } } */
-/* { dg-final { scan-assembler "ldmfd\tsp!, {r0, r1, r2, r3, r4, fp, ip, pc}\\^" } } */
+/* { dg-final { scan-assembler "push\t{r0, r1, r2, r3, r4, fp, ip, lr}" } } */
+/* { dg-final { scan-assembler "pop\t{r0, r1, r2, r3, r4, fp, ip, pc}\\^" } } */

gcc/testsuite/gcc.target/arm/interrupt-2.c

@@ -15,5 +15,5 @@ void test()
   foo = 0;
 }
 
-/* { dg-final { scan-assembler "stmfd\tsp!, {r0, r1, r2, r3, r4, r5, ip, lr}" } } */
-/* { dg-final { scan-assembler "ldmfd\tsp!, {r0, r1, r2, r3, r4, r5, ip, pc}\\^" } } */
+/* { dg-final { scan-assembler "push\t{r0, r1, r2, r3, r4, r5, ip, lr}" } } */
+/* { dg-final { scan-assembler "pop\t{r0, r1, r2, r3, r4, r5, ip, pc}\\^" } } */

gcc/testsuite/gcc.target/arm/unaligned-memcpy-4.c

@@ -14,7 +14,7 @@ void aligned_both (void)
 
 /* We know both src and dest to be aligned: expect multiword loads/stores.  */
 
-/* { dg-final { scan-assembler-times "ldmia" 1 { target { ! { arm_prefer_ldrd_strd } } } } } */
+/* { dg-final { scan-assembler-times "ldm" 1 { target { ! { arm_prefer_ldrd_strd } } } } } */
 /* { dg-final { scan-assembler-times "stmia" 1 { target { ! { arm_prefer_ldrd_strd } } } } } */
 /* { dg-final { scan-assembler "ldrd" { target { arm_prefer_ldrd_strd } } } } */
 /* { dg-final { scan-assembler-times "ldm" 0 { target { arm_prefer_ldrd_strd } } } } */