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Commit bab53516 by Sandra Loosemore Committed by Sandra Loosemore
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neon.md (UNSPEC_VABA): Delete. 

2010-07-02  Sandra Loosemore  <sandra@codesourcery.com>
	    Julian Brown  <julian@codesourcery.com>

	gcc/
	* config/arm/neon.md (UNSPEC_VABA): Delete.
	(UNSPEC_VABAL): Delete.
	(UNSPEC_VABS): Delete.
	(UNSPEC_VMUL_N): Delete.
	(adddi3_neon): New.
	(subdi3_neon): New.
	(mul<mode>3add<mode>_neon): Make the pattern named.
	(mul<mode>3neg<mode>add<mode>_neon): Likewise.
	(neon_vadd<mode>): Replace with define_expand, and move the remaining
	unspec parts...
	(neon_vadd<mode>_unspec): ...to this.
	(neon_vmla<mode>, neon_vmla<mode>_unspec): Likewise.
	(neon_vlms<mode>, neon_vmls<mode>_unspec): Likewise.
	(neon_vsub<mode>, neon_vsub<mode>_unspec): Likewise.
	(neon_vaba<mode>): Rewrite in terms of vabd.
	(neon_vabal<mode>): Rewrite in terms of vabdl.
	(neon_vabs<mode>): Rewrite without unspec.
	* config/arm/arm.md (*arm_adddi3): Disable for TARGET_NEON.
	(*arm_subdi3): Likewise.
	* config/arm/neon.ml (Vadd, Vsub): Split out 64-bit variants and add
	No_op attribute to disable assembly output checks.
	* config/arm/arm_neon.h: Regenerated.
	* doc/arm-neon-intrinsics.texi: Regenerated.

	gcc/testsuite/
	* gcc.target/arm/neon/vadds64.c: Regenerated.
	* gcc.target/arm/neon/vaddu64.c: Regenerated.
	* gcc.target/arm/neon/vsubs64.c: Regenerated.
	* gcc.target/arm/neon/vsubu64.c: Regenerated.
	* gcc.target/arm/neon-vmla-1.c: Add -ffast-math to options.
	* gcc.target/arm/neon-vmls-1.c: Likewise.
	* gcc.target/arm/neon-vsubs64.c: New execution test.
	* gcc.target/arm/neon-vsubu64.c: New execution test.
	* gcc.target/arm/neon-vadds64.c: New execution test.
	* gcc.target/arm/neon-vaddu64.c: New execution test.

Co-Authored-By: Julian Brown <julian@codesourcery.com>

From-SVN: r161762
parent b614e566
Showing with 155 additions and 35 deletions
gcc/ChangeLog
2010-07-02 Sandra Loosemore <sandra@codesourcery.com>
Julian Brown <julian@codesourcery.com>
* config/arm/neon.md (UNSPEC_VABA): Delete.
(UNSPEC_VABAL): Delete.
(UNSPEC_VABS): Delete.
(UNSPEC_VMUL_N): Delete.
(adddi3_neon): New.
(subdi3_neon): New.
(mul<mode>3add<mode>_neon): Make the pattern named.
(mul<mode>3neg<mode>add<mode>_neon): Likewise.
(neon_vadd<mode>): Replace with define_expand, and move the remaining
unspec parts...
(neon_vadd<mode>_unspec): ...to this.
(neon_vmla<mode>, neon_vmla<mode>_unspec): Likewise.
(neon_vlms<mode>, neon_vmls<mode>_unspec): Likewise.
(neon_vsub<mode>, neon_vsub<mode>_unspec): Likewise.
(neon_vaba<mode>): Rewrite in terms of vabd.
(neon_vabal<mode>): Rewrite in terms of vabdl.
(neon_vabs<mode>): Rewrite without unspec.
* config/arm/arm.md (*arm_adddi3): Disable for TARGET_NEON.
(*arm_subdi3): Likewise.
* config/arm/neon.ml (Vadd, Vsub): Split out 64-bit variants and add
No_op attribute to disable assembly output checks.
* config/arm/arm_neon.h: Regenerated.
* doc/arm-neon-intrinsics.texi: Regenerated.
2010-07-02 Jan Hubicka <jh@suse.cz>
* ipa-split.c (split_function): For aggregate values set return_slot_opt;
......
gcc/config/arm/arm.md
......@@ -495,9 +495,10 @@
(plus:DI (match_operand:DI 1 "s_register_operand" "%0, 0")
(match_operand:DI 2 "s_register_operand" "r, 0")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)"
"TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK) && !TARGET_NEON"
"#"
"TARGET_32BIT && reload_completed"
"TARGET_32BIT && reload_completed
&& ! (TARGET_NEON && IS_VFP_REGNUM (REGNO (operands[0])))"
[(parallel [(set (reg:CC_C CC_REGNUM)
(compare:CC_C (plus:SI (match_dup 1) (match_dup 2))
(match_dup 1)))
......@@ -994,7 +995,7 @@
(minus:DI (match_operand:DI 1 "s_register_operand" "0,r,0")
(match_operand:DI 2 "s_register_operand" "r,0,0")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_32BIT"
"TARGET_32BIT && !TARGET_NEON"
"subs\\t%Q0, %Q1, %Q2\;sbc\\t%R0, %R1, %R2"
[(set_attr "conds" "clob")
(set_attr "length" "8")]
......
gcc/config/arm/arm_neon.h
......@@ -414,12 +414,6 @@ vadd_s32 (int32x2_t __a, int32x2_t __b)
return (int32x2_t)__builtin_neon_vaddv2si (__a, __b, 1);
}
__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
vadd_s64 (int64x1_t __a, int64x1_t __b)
{
return (int64x1_t)__builtin_neon_vadddi (__a, __b, 1);
}
__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
vadd_f32 (float32x2_t __a, float32x2_t __b)
{
......@@ -444,6 +438,12 @@ vadd_u32 (uint32x2_t __a, uint32x2_t __b)
return (uint32x2_t)__builtin_neon_vaddv2si ((int32x2_t) __a, (int32x2_t) __b, 0);
}
__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
vadd_s64 (int64x1_t __a, int64x1_t __b)
{
return (int64x1_t)__builtin_neon_vadddi (__a, __b, 1);
}
__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
vadd_u64 (uint64x1_t __a, uint64x1_t __b)
{
......@@ -1368,12 +1368,6 @@ vsub_s32 (int32x2_t __a, int32x2_t __b)
return (int32x2_t)__builtin_neon_vsubv2si (__a, __b, 1);
}
__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
vsub_s64 (int64x1_t __a, int64x1_t __b)
{
return (int64x1_t)__builtin_neon_vsubdi (__a, __b, 1);
}
__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
vsub_f32 (float32x2_t __a, float32x2_t __b)
{
......@@ -1398,6 +1392,12 @@ vsub_u32 (uint32x2_t __a, uint32x2_t __b)
return (uint32x2_t)__builtin_neon_vsubv2si ((int32x2_t) __a, (int32x2_t) __b, 0);
}
__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
vsub_s64 (int64x1_t __a, int64x1_t __b)
{
return (int64x1_t)__builtin_neon_vsubdi (__a, __b, 1);
}
__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
vsub_u64 (uint64x1_t __a, uint64x1_t __b)
{
......
gcc/config/arm/neon.ml
......@@ -709,7 +709,8 @@ let pf_su_8_64 = P8 :: P16 :: F32 :: su_8_64
let ops =
[
(* Addition. *)
Vadd, [], All (3, Dreg), "vadd", sign_invar_2, F32 :: su_8_64;
Vadd, [], All (3, Dreg), "vadd", sign_invar_2, F32 :: su_8_32;
Vadd, [No_op], All (3, Dreg), "vadd", sign_invar_2, [S64; U64];
Vadd, [], All (3, Qreg), "vaddQ", sign_invar_2, F32 :: su_8_64;
Vadd, [], Long, "vaddl", elts_same_2, su_8_32;
Vadd, [], Wide, "vaddw", elts_same_2, su_8_32;
......@@ -758,7 +759,8 @@ let ops =
Vmls, [Saturating; Doubling], Long, "vqdmlsl", elts_same_io, [S16; S32];
(* Subtraction. *)
Vsub, [], All (3, Dreg), "vsub", sign_invar_2, F32 :: su_8_64;
Vsub, [], All (3, Dreg), "vsub", sign_invar_2, F32 :: su_8_32;
Vsub, [No_op], All (3, Dreg), "vsub", sign_invar_2, [S64; U64];
Vsub, [], All (3, Qreg), "vsubQ", sign_invar_2, F32 :: su_8_64;
Vsub, [], Long, "vsubl", elts_same_2, su_8_32;
Vsub, [], Wide, "vsubw", elts_same_2, su_8_32;
......
gcc/doc/arm-neon-intrinsics.texi
......@@ -43,20 +43,18 @@
@itemize @bullet
@item uint64x1_t vadd_u64 (uint64x1_t, uint64x1_t)
@*@emph{Form of expected instruction(s):} @code{vadd.i64 @var{d0}, @var{d0}, @var{d0}}
@item float32x2_t vadd_f32 (float32x2_t, float32x2_t)
@*@emph{Form of expected instruction(s):} @code{vadd.f32 @var{d0}, @var{d0}, @var{d0}}
@end itemize
@itemize @bullet
@item int64x1_t vadd_s64 (int64x1_t, int64x1_t)
@*@emph{Form of expected instruction(s):} @code{vadd.i64 @var{d0}, @var{d0}, @var{d0}}
@item uint64x1_t vadd_u64 (uint64x1_t, uint64x1_t)
@end itemize
@itemize @bullet
@item float32x2_t vadd_f32 (float32x2_t, float32x2_t)
@*@emph{Form of expected instruction(s):} @code{vadd.f32 @var{d0}, @var{d0}, @var{d0}}
@item int64x1_t vadd_s64 (int64x1_t, int64x1_t)
@end itemize
......@@ -1013,20 +1011,18 @@
@itemize @bullet
@item uint64x1_t vsub_u64 (uint64x1_t, uint64x1_t)
@*@emph{Form of expected instruction(s):} @code{vsub.i64 @var{d0}, @var{d0}, @var{d0}}
@item float32x2_t vsub_f32 (float32x2_t, float32x2_t)
@*@emph{Form of expected instruction(s):} @code{vsub.f32 @var{d0}, @var{d0}, @var{d0}}
@end itemize
@itemize @bullet
@item int64x1_t vsub_s64 (int64x1_t, int64x1_t)
@*@emph{Form of expected instruction(s):} @code{vsub.i64 @var{d0}, @var{d0}, @var{d0}}
@item uint64x1_t vsub_u64 (uint64x1_t, uint64x1_t)
@end itemize
@itemize @bullet
@item float32x2_t vsub_f32 (float32x2_t, float32x2_t)
@*@emph{Form of expected instruction(s):} @code{vsub.f32 @var{d0}, @var{d0}, @var{d0}}
@item int64x1_t vsub_s64 (int64x1_t, int64x1_t)
@end itemize
......
gcc/testsuite/ChangeLog
2010-07-02 Sandra Loosemore <sandra@codesourcery.com>
Julian Brown <julian@codesourcery.com>
* gcc.target/arm/neon/vadds64.c: Regenerated.
* gcc.target/arm/neon/vaddu64.c: Regenerated.
* gcc.target/arm/neon/vsubs64.c: Regenerated.
* gcc.target/arm/neon/vsubu64.c: Regenerated.
* gcc.target/arm/neon-vmla-1.c: Add -ffast-math to options.
* gcc.target/arm/neon-vmls-1.c: Likewise.
* gcc.target/arm/neon-vsubs64.c: New execution test.
* gcc.target/arm/neon-vsubu64.c: New execution test.
* gcc.target/arm/neon-vadds64.c: New execution test.
* gcc.target/arm/neon-vaddu64.c: New execution test.
2010-07-02 Sandra Loosemore <sandra@codesourcery.com>
* gcc.target/arm/neon-vands64.c: New.
* gcc.target/arm/neon-vandu64.c: New.
......
gcc/testsuite/gcc.target/arm/neon-vadds64.c 0 → 100644
/* Test the `vadd_s64' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_hw } */
/* { dg-options "-O0" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include <stdlib.h>
int main (void)
{
int64x1_t out_int64x1_t = 0;
int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeef00000000LL;
int64x1_t arg1_int64x1_t = (int64x1_t)0x00000000deadbeefLL;
out_int64x1_t = vadd_s64 (arg0_int64x1_t, arg1_int64x1_t);
if (out_int64x1_t != (int64x1_t)0xdeadbeefdeadbeefLL)
abort();
return 0;
}
gcc/testsuite/gcc.target/arm/neon-vaddu64.c 0 → 100644
/* Test the `vadd_u64' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_hw } */
/* { dg-options "-O0" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include <stdlib.h>
int main (void)
{
uint64x1_t out_uint64x1_t = 0;
uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeef00000000LL;
uint64x1_t arg1_uint64x1_t = (uint64x1_t)0x00000000deadbeefLL;
out_uint64x1_t = vadd_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
if (out_uint64x1_t != (uint64x1_t)0xdeadbeefdeadbeefLL)
abort();
return 0;
}
gcc/testsuite/gcc.target/arm/neon-vmla-1.c
/* { dg-require-effective-target arm_neon_hw } */
/* { dg-options "-O2 -ftree-vectorize" } */
/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */
/* { dg-add-options arm_neon } */
/* { dg-final { scan-assembler "vmla\\.f32" } } */
......
gcc/testsuite/gcc.target/arm/neon-vmls-1.c
/* { dg-require-effective-target arm_neon_hw } */
/* { dg-options "-O2 -ftree-vectorize" } */
/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */
/* { dg-add-options arm_neon } */
/* { dg-final { scan-assembler "vmls\\.f32" } } */
......
gcc/testsuite/gcc.target/arm/neon-vsubs64.c 0 → 100644
/* Test the `vsub_s64' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_hw } */
/* { dg-options "-O0" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include <stdlib.h>
int main (void)
{
int64x1_t out_int64x1_t = 0;
int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeefdeadbeefLL;
int64x1_t arg1_int64x1_t = (int64x1_t)0x0000beefdead0000LL;
out_int64x1_t = vsub_s64 (arg0_int64x1_t, arg1_int64x1_t);
if (out_int64x1_t != (int64x1_t)0xdead00000000beefLL)
abort();
return 0;
}
gcc/testsuite/gcc.target/arm/neon-vsubu64.c 0 → 100644
/* Test the `vsub_u64' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_hw } */
/* { dg-options "-O0" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include <stdlib.h>
int main (void)
{
uint64x1_t out_uint64x1_t = 0;
uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeefdeadbeefLL;
uint64x1_t arg1_uint64x1_t = (uint64x1_t)0x0000beefdead0000LL;
out_uint64x1_t = vsub_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
if (out_uint64x1_t != (uint64x1_t)0xdead00000000beefLL)
abort();
return 0;
}
gcc/testsuite/gcc.target/arm/neon/vadds64.c
......@@ -17,5 +17,4 @@ void test_vadds64 (void)
out_int64x1_t = vadd_s64 (arg0_int64x1_t, arg1_int64x1_t);
}
/* { dg-final { scan-assembler "vadd\.i64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */
gcc/testsuite/gcc.target/arm/neon/vaddu64.c
......@@ -17,5 +17,4 @@ void test_vaddu64 (void)
out_uint64x1_t = vadd_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
}
/* { dg-final { scan-assembler "vadd\.i64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */
gcc/testsuite/gcc.target/arm/neon/vsubs64.c
......@@ -17,5 +17,4 @@ void test_vsubs64 (void)
out_int64x1_t = vsub_s64 (arg0_int64x1_t, arg1_int64x1_t);
}
/* { dg-final { scan-assembler "vsub\.i64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */
gcc/testsuite/gcc.target/arm/neon/vsubu64.c
......@@ -17,5 +17,4 @@ void test_vsubu64 (void)
out_uint64x1_t = vsub_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
}
/* { dg-final { scan-assembler "vsub\.i64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */
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