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Commit ba081b77 by James Greenhalgh Committed by James Greenhalgh
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[AArch64] Improve vst4_lane intrinsics 

gcc/

	* config/aarch64/aarch64-builtins.c
	(aarch64_types_storestruct_lane_qualifiers): New.
	(TYPES_STORESTRUCT_LANE): Likewise.
	* config/aarch64/aarch64-simd-builtins.def (st2_lane): New.
	(st3_lane): Likewise.
	(st4_lane): Likewise.
	* config/aarch64/aarch64-simd.md (vec_store_lanesoi_lane<mode>): New.
	(vec_store_lanesci_lane<mode>): Likewise.
	(vec_store_lanesxi_lane<mode>): Likewise.
	(aarch64_st2_lane<VQ:mode>): Likewise.
	(aarch64_st3_lane<VQ:mode>): Likewise.
	(aarch64_st4_lane<VQ:mode>): Likewise.
	* config/aarch64/aarch64.md (unspec): Add UNSPEC_ST{2,3,4}_LANE.
	* config/aarch64/arm_neon.h
	(__ST2_LANE_FUNC): Rewrite using builtins, update use points to
	use new macro arguments.
	(__ST3_LANE_FUNC): Likewise.
	(__ST4_LANE_FUNC): Likewise.
	* config/aarch64/iterators.md (V_TWO_ELEM): New.
	(V_THREE_ELEM): Likewise.
	(V_FOUR_ELEM): Likewise.

From-SVN: r209880
parent 1bc6d43c
Showing with 146 additions and 0 deletions
gcc/ChangeLog
2014-04-28 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_types_storestruct_lane_qualifiers): New.
(TYPES_STORESTRUCT_LANE): Likewise.
* config/aarch64/aarch64-simd-builtins.def (st2_lane): New.
(st3_lane): Likewise.
(st4_lane): Likewise.
* config/aarch64/aarch64-simd.md (vec_store_lanesoi_lane<mode>): New.
(vec_store_lanesci_lane<mode>): Likewise.
(vec_store_lanesxi_lane<mode>): Likewise.
(aarch64_st2_lane<VQ:mode>): Likewise.
(aarch64_st3_lane<VQ:mode>): Likewise.
(aarch64_st4_lane<VQ:mode>): Likewise.
* config/aarch64/aarch64.md (unspec): Add UNSPEC_ST{2,3,4}_LANE.
* config/aarch64/arm_neon.h
(__ST2_LANE_FUNC): Rewrite using builtins, update use points to
use new macro arguments.
(__ST3_LANE_FUNC): Likewise.
(__ST4_LANE_FUNC): Likewise.
* config/aarch64/iterators.md (V_TWO_ELEM): New.
(V_THREE_ELEM): Likewise.
(V_FOUR_ELEM): Likewise.
2014-04-28 David Malcolm <dmalcolm@redhat.com>
* doc/gimple.texi: Replace the description of the now-defunct
......
gcc/config/aarch64/aarch64-builtins.c
......@@ -246,6 +246,11 @@ aarch64_types_store1_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_void, qualifier_pointer_map_mode, qualifier_none };
#define TYPES_STORE1 (aarch64_types_store1_qualifiers)
#define TYPES_STORESTRUCT (aarch64_types_store1_qualifiers)
static enum aarch64_type_qualifiers
aarch64_types_storestruct_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_void, qualifier_pointer_map_mode,
qualifier_none, qualifier_none };
#define TYPES_STORESTRUCT_LANE (aarch64_types_storestruct_lane_qualifiers)
#define CF0(N, X) CODE_FOR_aarch64_##N##X
#define CF1(N, X) CODE_FOR_##N##X##1
......
gcc/config/aarch64/aarch64-simd-builtins.def
......@@ -118,6 +118,10 @@
BUILTIN_VQ (STORESTRUCT, st3, 0)
BUILTIN_VQ (STORESTRUCT, st4, 0)
BUILTIN_VQ (STORESTRUCT_LANE, st2_lane, 0)
BUILTIN_VQ (STORESTRUCT_LANE, st3_lane, 0)
BUILTIN_VQ (STORESTRUCT_LANE, st4_lane, 0)
BUILTIN_VQW (BINOP, saddl2, 0)
BUILTIN_VQW (BINOP, uaddl2, 0)
BUILTIN_VQW (BINOP, ssubl2, 0)
......
gcc/config/aarch64/aarch64-simd.md
......@@ -3686,6 +3686,17 @@
[(set_attr "type" "neon_store2_2reg<q>")]
)
(define_insn "vec_store_lanesoi_lane<mode>"
[(set (match_operand:<V_TWO_ELEM> 0 "aarch64_simd_struct_operand" "=Utv")
(unspec:<V_TWO_ELEM> [(match_operand:OI 1 "register_operand" "w")
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
(match_operand:SI 2 "immediate_operand" "i")]
UNSPEC_ST2_LANE))]
"TARGET_SIMD"
"st2\\t{%S1.<Vetype> - %T1.<Vetype>}[%2], %0"
[(set_attr "type" "neon_store3_one_lane<q>")]
)
(define_insn "vec_load_lanesci<mode>"
[(set (match_operand:CI 0 "register_operand" "=w")
(unspec:CI [(match_operand:CI 1 "aarch64_simd_struct_operand" "Utv")
......@@ -3706,6 +3717,17 @@
[(set_attr "type" "neon_store3_3reg<q>")]
)
(define_insn "vec_store_lanesci_lane<mode>"
[(set (match_operand:<V_THREE_ELEM> 0 "aarch64_simd_struct_operand" "=Utv")
(unspec:<V_THREE_ELEM> [(match_operand:CI 1 "register_operand" "w")
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
(match_operand:SI 2 "immediate_operand" "i")]
UNSPEC_ST3_LANE))]
"TARGET_SIMD"
"st3\\t{%S1.<Vetype> - %U1.<Vetype>}[%2], %0"
[(set_attr "type" "neon_store3_one_lane<q>")]
)
(define_insn "vec_load_lanesxi<mode>"
[(set (match_operand:XI 0 "register_operand" "=w")
(unspec:XI [(match_operand:XI 1 "aarch64_simd_struct_operand" "Utv")
......@@ -3726,6 +3748,17 @@
[(set_attr "type" "neon_store4_4reg<q>")]
)
(define_insn "vec_store_lanesxi_lane<mode>"
[(set (match_operand:<V_FOUR_ELEM> 0 "aarch64_simd_struct_operand" "=Utv")
(unspec:<V_FOUR_ELEM> [(match_operand:XI 1 "register_operand" "w")
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
(match_operand:SI 2 "immediate_operand" "i")]
UNSPEC_ST4_LANE))]
"TARGET_SIMD"
"st4\\t{%S1.<Vetype> - %V1.<Vetype>}[%2], %0"
[(set_attr "type" "neon_store4_one_lane<q>")]
)
;; Reload patterns for AdvSIMD register list operands.
(define_expand "mov<mode>"
......@@ -4220,6 +4253,57 @@
DONE;
})
(define_expand "aarch64_st2_lane<VQ:mode>"
[(match_operand:DI 0 "register_operand" "r")
(match_operand:OI 1 "register_operand" "w")
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
(match_operand:SI 2 "immediate_operand")]
"TARGET_SIMD"
{
enum machine_mode mode = <V_TWO_ELEM>mode;
rtx mem = gen_rtx_MEM (mode, operands[0]);
operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2])));
emit_insn (gen_vec_store_lanesoi_lane<VQ:mode> (mem,
operands[1],
operands[2]));
DONE;
})
(define_expand "aarch64_st3_lane<VQ:mode>"
[(match_operand:DI 0 "register_operand" "r")
(match_operand:CI 1 "register_operand" "w")
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
(match_operand:SI 2 "immediate_operand")]
"TARGET_SIMD"
{
enum machine_mode mode = <V_THREE_ELEM>mode;
rtx mem = gen_rtx_MEM (mode, operands[0]);
operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2])));
emit_insn (gen_vec_store_lanesci_lane<VQ:mode> (mem,
operands[1],
operands[2]));
DONE;
})
(define_expand "aarch64_st4_lane<VQ:mode>"
[(match_operand:DI 0 "register_operand" "r")
(match_operand:XI 1 "register_operand" "w")
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
(match_operand:SI 2 "immediate_operand")]
"TARGET_SIMD"
{
enum machine_mode mode = <V_FOUR_ELEM>mode;
rtx mem = gen_rtx_MEM (mode, operands[0]);
operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2])));
emit_insn (gen_vec_store_lanesxi_lane<VQ:mode> (mem,
operands[1],
operands[2]));
DONE;
})
(define_expand "aarch64_st1<VALL:mode>"
[(match_operand:DI 0 "register_operand")
(match_operand:VALL 1 "register_operand")]
......
gcc/config/aarch64/aarch64.md
......@@ -98,6 +98,9 @@
UNSPEC_ST2
UNSPEC_ST3
UNSPEC_ST4
UNSPEC_ST2_LANE
UNSPEC_ST3_LANE
UNSPEC_ST4_LANE
UNSPEC_TLS
UNSPEC_TLSDESC
UNSPEC_USHL_2S
......
gcc/config/aarch64/iterators.md
......@@ -564,6 +564,32 @@
(define_mode_attr VSTRUCT_DREG [(OI "TI") (CI "EI") (XI "OI")])
;; Mode of pair of elements for each vector mode, to define transfer
;; size for structure lane/dup loads and stores.
(define_mode_attr V_TWO_ELEM [(V8QI "HI") (V16QI "HI")
(V4HI "SI") (V8HI "SI")
(V2SI "V2SI") (V4SI "V2SI")
(DI "V2DI") (V2DI "V2DI")
(V2SF "V2SF") (V4SF "V2SF")
(DF "V2DI") (V2DF "V2DI")])
;; Similar, for three elements.
(define_mode_attr V_THREE_ELEM [(V8QI "BLK") (V16QI "BLK")
(V4HI "BLK") (V8HI "BLK")
(V2SI "BLK") (V4SI "BLK")
(DI "EI") (V2DI "EI")
(V2SF "BLK") (V4SF "BLK")
(DF "EI") (V2DF "EI")])
;; Similar, for four elements.
(define_mode_attr V_FOUR_ELEM [(V8QI "SI") (V16QI "SI")
(V4HI "V4HI") (V8HI "V4HI")
(V2SI "V4SI") (V4SI "V4SI")
(DI "OI") (V2DI "OI")
(V2SF "V4SF") (V4SF "V4SF")
(DF "OI") (V2DF "OI")])
;; Mode for atomic operation suffixes
(define_mode_attr atomic_sfx
[(QI "b") (HI "h") (SI "") (DI "")])
......
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