[AArch64] Fix order of modes to lroundmn2 standard names.

gcc/
	* config/aarch64/aarch64-simd.md
	(l<fcvt_pattern><su_optab><fcvt_target><VDQF:mode>2): Rename to...
	(l<fcvt_pattern><su_optab><VDQF:mode><fcvt_target>2): ... This.

From-SVN: r198397

gcc/ChangeLog

 2013-04-29  James Greenhalgh  <james.greenhalgh@arm.com>
 
+	* config/aarch64/aarch64-simd.md
+	(l<fcvt_pattern><su_optab><fcvt_target><VDQF:mode>2): Rename to...
+	(l<fcvt_pattern><su_optab><VDQF:mode><fcvt_target>2): ... This.
+
+2013-04-29  James Greenhalgh  <james.greenhalgh@arm.com>
+
 	* config/aarch64/arm_neon.h (vrndq<a,m,n,p>_f<32, 64>): Rename to...
 	(vrnd<a,m,n,p>q_f<32, 64>): ...This, implement using builtin.
 	(vrnd<a,m,n,p>_f32): Implement using builtins.

gcc/config/aarch64/aarch64-simd.md

@@ -1257,7 +1257,7 @@
 
 ;; Vector versions of the fcvt standard patterns.
 ;; Expands to lbtrunc, lround, lceil, lfloor
-(define_expand "l<fcvt_pattern><su_optab><fcvt_target><VDQF:mode>2"
+(define_expand "l<fcvt_pattern><su_optab><VDQF:mode><fcvt_target>2"
   [(set (match_operand:<FCVT_TARGET> 0 "register_operand")
 	(FIXUORS:<FCVT_TARGET> (unspec:<FCVT_TARGET>
 			       [(match_operand:VDQF 1 "register_operand")]