Commit b890a441 by Alexandre Oliva Committed by Jeff Law

re PR target/69634 (-fcompare-debug failure (length) with -O2 -fno-dce…

re PR target/69634 (-fcompare-debug failure (length) with -O2 -fno-dce -fschedule-insns -fno-tree-vrp @ i686)

2016-02-11  Alexandre Oliva  <aoliva@redhat.com>

	PR target/69634
	* regstat.c (regstat_bb_compute_calls_crossed): Disregard
	debug insns.

	PR target/69634
	* gcc.dg/pr69634.c: New.

From-SVN: r233250
parent 4849c1c7
2016-02-11 Alexandre Oliva <aoliva@redhat.com>
PR target/69634
* regstat.c (regstat_bb_compute_calls_crossed): Disregard
debug insns.
2016-02-09 Uros Bizjak <ubizjak@gmail.com> 2016-02-09 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.md (insv<mode>_1): Use gen_int_mode to * config/i386/i386.md (insv<mode>_1): Use gen_int_mode to
......
...@@ -444,7 +444,7 @@ regstat_bb_compute_calls_crossed (unsigned int bb_index, bitmap live) ...@@ -444,7 +444,7 @@ regstat_bb_compute_calls_crossed (unsigned int bb_index, bitmap live)
struct df_insn_info *insn_info = DF_INSN_INFO_GET (insn); struct df_insn_info *insn_info = DF_INSN_INFO_GET (insn);
unsigned int regno; unsigned int regno;
if (!INSN_P (insn)) if (!NONDEBUG_INSN_P (insn))
continue; continue;
/* Process the defs. */ /* Process the defs. */
......
2016-02-11 Alexandre Oliva <aoliva@redhat.com>
PR target/69634
* gcc.dg/pr69634.c: New.
2016-02-09 Richard Biener <rguenther@suse.de> 2016-02-09 Richard Biener <rguenther@suse.de>
* gcc.dg/vect/vect-mask-store-move-1.c: Add missing space. * gcc.dg/vect/vect-mask-store-move-1.c: Add missing space.
......
/* { dg-do compile } */
/* { dg-options "-O2 -fno-dce -fschedule-insns -fno-tree-vrp -fcompare-debug" } */
/* { dg-additional-options "-Wno-psabi -mno-sse" { target i?86-*-* x86_64-*-* } } */
typedef unsigned short u16;
typedef short v16u16 __attribute__ ((vector_size (16)));
typedef unsigned v16u32 __attribute__ ((vector_size (16)));
typedef unsigned long long v16u64 __attribute__ ((vector_size (16)));
u16
foo(u16 u16_1, v16u16 v16u16_0, v16u32 v16u64_0, v16u16 v16u16_1, v16u32 v16u32_1, v16u64 v16u64_1)
{
v16u64_1 /= (v16u64){~v16u32_1[1]};
u16_1 = 0;
u16_1 /= v16u32_1[2];
v16u64_1 -= (v16u64) v16u16_1;
u16_1 >>= 1;
u16_1 -= ~0;
v16u16_1 /= (v16u16){~u16_1, 1 - v16u64_0[0], 0xffb6};
return u16_1 + v16u16_0[1] + v16u16_1[3] + v16u64_1[0] + v16u64_1[1];
}
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